| Message ID | 8dd000fd9040804ec520b76de1b026747e16fc2c.1704788539.git.ysato@users.sourceforge.jp (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Device Tree support for SH7751 based board | expand |
Hi Sato-san, Thanks for your patch! On Tue, Jan 9, 2024 at 9:24 AM Yoshinori Sato <ysato@users.sourceforge.jp> wrote: > SH7750 CPG Clock output define. Please improve the patch description. > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml > @@ -0,0 +1,103 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas SH7750/7751 Clock Pulse Generator (CPG) > + > +maintainers: > + - Yoshinori Sato <ysato@users.sourceforge.jp> > + > +description: > + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It > + includes PLLs, and variable ratio dividers. > + > + The CPG may also provide a Clock Domain for SoC devices, in combination with > + the CPG Module Stop (MSTP) Clocks. > + > +properties: > + compatible: > + enum: > + - renesas,sh7750-cpg # SH7750 > + - renesas,sh7750s-cpg # SH775S > + - renesas,sh7750r-cpg # SH7750R > + - renesas,sh7751-cpg # SH7751 > + - renesas,sh7751r-cpg # SH7751R > + > + reg: true > + > + reg-names: true > + > + clocks: true clocks: maxItems: 1 > + > + clock-names: true clock-names: const: extal > +examples: > + - | > + #include <dt-bindings/clock/sh7750-cpg.h> > + cpg: clock-controller@ffc00000 { > + #clock-cells = <1>; > + #power-domain-cells = <0>; > + compatible = "renesas,sh7751r-cpg"; > + clocks = <&xtal>; > + clock-names = "xtal"; "extal" "xtal" is an output pin, connected to a crystal resonator. "extal" is the clock input put (either crystal resonator or exteral clock input. > + reg = <0xffc00000 20>, <0xfe0a0000 16>; > + reg-names = "FRQCR", "CLKSTP00"; > + renesas,mode = <0>; > + }; > diff --git a/include/dt-bindings/clock/sh7750-cpg.h b/include/dt-bindings/clock/sh7750-cpg.h > new file mode 100644 > index 000000000000..17d5a8076aac > --- /dev/null > +++ b/include/dt-bindings/clock/sh7750-cpg.h > @@ -0,0 +1,26 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > + * > + * Copyright 2023 Yoshinori Sato > + */ > + > +#ifndef __DT_BINDINGS_CLOCK_SH7750_H__ > +#define __DT_BINDINGS_CLOCK_SH7750_H__ > + > +#define SH7750_CPG_PLLOUT 0 > + > +#define SH7750_CPG_FCK 1 PCK? > +#define SH7750_CPG_BCK 2 > +#define SH7750_CPG_ICK 3 Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file mode 100644 index 000000000000..da0b837c1123 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7750/7751 Clock Pulse Generator (CPG) + +maintainers: + - Yoshinori Sato <ysato@users.sourceforge.jp> + +description: + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It + includes PLLs, and variable ratio dividers. + + The CPG may also provide a Clock Domain for SoC devices, in combination with + the CPG Module Stop (MSTP) Clocks. + +properties: + compatible: + enum: + - renesas,sh7750-cpg # SH7750 + - renesas,sh7750s-cpg # SH775S + - renesas,sh7750r-cpg # SH7750R + - renesas,sh7751-cpg # SH7751 + - renesas,sh7751r-cpg # SH7751R + + reg: true + + reg-names: true + + clocks: true + + clock-names: true + + '#clock-cells': + const: 1 + + renesas,mode: + description: Board-specific settings of the MD[0-2] pins on SoC + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 6 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#clock-cells' + +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,sh7750-cpg + - renesas,sh7750s-cpg + then: + properties: + reg: + maxItems: 1 + reg-names: + items: + - const: FRQCR + + - if: + properties: + compatible: + contains: + enum: + - renesas,sh7750r-cpg + - renesas,sh7751-cpg + - renesas,sh7751r-cpg + then: + properties: + reg: + maxItems: 2 + reg-names: + items: + - const: FRQCR + - const: CLKSTP00 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sh7750-cpg.h> + cpg: clock-controller@ffc00000 { + #clock-cells = <1>; + #power-domain-cells = <0>; + compatible = "renesas,sh7751r-cpg"; + clocks = <&xtal>; + clock-names = "xtal"; + reg = <0xffc00000 20>, <0xfe0a0000 16>; + reg-names = "FRQCR", "CLKSTP00"; + renesas,mode = <0>; + }; diff --git a/include/dt-bindings/clock/sh7750-cpg.h b/include/dt-bindings/clock/sh7750-cpg.h new file mode 100644 index 000000000000..17d5a8076aac --- /dev/null +++ b/include/dt-bindings/clock/sh7750-cpg.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright 2023 Yoshinori Sato + */ + +#ifndef __DT_BINDINGS_CLOCK_SH7750_H__ +#define __DT_BINDINGS_CLOCK_SH7750_H__ + +#define SH7750_CPG_PLLOUT 0 + +#define SH7750_CPG_FCK 1 +#define SH7750_CPG_BCK 2 +#define SH7750_CPG_ICK 3 + +#define SH7750_MSTP_SCI 4 +#define SH7750_MSTP_RTC 5 +#define SH7750_MSTP_TMU012 6 +#define SH7750_MSTP_SCIF 7 +#define SH7750_MSTP_DMAC 8 +#define SH7750_MSTP_UBC 9 +#define SH7750_MSTP_SQ 10 +#define SH7750_CSTP_INTC 11 +#define SH7750_CSTP_TMU34 12 +#define SH7750_CSTP_PCIC 13 + +#endif
SH7750 CPG Clock output define. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> --- .../bindings/clock/renesas,sh7750-cpg.yaml | 103 ++++++++++++++++++ include/dt-bindings/clock/sh7750-cpg.h | 26 +++++ 2 files changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml create mode 100644 include/dt-bindings/clock/sh7750-cpg.h