| Message ID | 20231013181712.2128037-1-jernej.skrabec@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: sunxi-ng: h6: Reparent CPUX during PLL CPUX rate change | expand |
On Sat, Oct 14, 2023 at 2:17 AM Jernej Skrabec <jernej.skrabec@gmail.com> wrote: > > While PLL CPUX clock rate change when CPU is running from it works in > vast majority of cases, now and then it causes instability. This leads > to system crashes and other undefined behaviour. After a lot of testing > (30+ hours) while also doing a lot of frequency switches, we can't > observe any instability issues anymore when doing reparenting to stable > clock like 24 MHz oscillator. > > Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") > Reported-by: Chad Wagner <wagnerch42@gmail.com> > Link: https://forum.libreelec.tv/thread/27295-orange-pi-3-lts-freezes/ > Tested-by: Chad Wagner <wagnerch42@gmail.com> > Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Dne sobota, 2. marec 2024 ob 12:42:11 GMT +2 je Chen-Yu Tsai napisal(a): > On Sat, Oct 14, 2023 at 2:17 AM Jernej Skrabec <jernej.skrabec@gmail.com> wrote: > > > > While PLL CPUX clock rate change when CPU is running from it works in > > vast majority of cases, now and then it causes instability. This leads > > to system crashes and other undefined behaviour. After a lot of testing > > (30+ hours) while also doing a lot of frequency switches, we can't > > observe any instability issues anymore when doing reparenting to stable > > clock like 24 MHz oscillator. > > > > Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") > > Reported-by: Chad Wagner <wagnerch42@gmail.com> > > Link: https://forum.libreelec.tv/thread/27295-orange-pi-3-lts-freezes/ > > Tested-by: Chad Wagner <wagnerch42@gmail.com> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> > > Reviewed-by: Chen-Yu Tsai <wens@csie.org> > Applied. Best regards, Jernej
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index 42568c616181..892df807275c 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c @@ -1181,11 +1181,18 @@ static const u32 usb2_clk_regs[] = { SUN50I_H6_USB3_CLK_REG, }; +static struct ccu_mux_nb sun50i_h6_cpu_nb = { + .common = &cpux_clk.common, + .cm = &cpux_clk.mux, + .delay_us = 1, + .bypass_index = 0, /* index of 24 MHz oscillator */ +}; + static int sun50i_h6_ccu_probe(struct platform_device *pdev) { void __iomem *reg; + int i, ret; u32 val; - int i; reg = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(reg)) @@ -1252,7 +1259,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) val |= BIT(24); writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG); - return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc); + ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc); + if (ret) + return ret; + + /* Reparent CPU during PLL CPUX rate changes */ + ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, + &sun50i_h6_cpu_nb); + + return 0; } static const struct of_device_id sun50i_h6_ccu_ids[] = {
While PLL CPUX clock rate change when CPU is running from it works in vast majority of cases, now and then it causes instability. This leads to system crashes and other undefined behaviour. After a lot of testing (30+ hours) while also doing a lot of frequency switches, we can't observe any instability issues anymore when doing reparenting to stable clock like 24 MHz oscillator. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Reported-by: Chad Wagner <wagnerch42@gmail.com> Link: https://forum.libreelec.tv/thread/27295-orange-pi-3-lts-freezes/ Tested-by: Chad Wagner <wagnerch42@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> --- drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)