| Message ID | 20240304-pinephone-pll-fixes-v3-1-94ab828f269a@oltmanns.dev (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Pinephone video out fixes (flipping between two frames) | expand |
On Mon, Mar 04, 2024 at 08:29:17AM +0100, Frank Oltmanns wrote: > The Allwinner SoC's typically have an upper and lower limit for their > clocks' rates. Up until now, support for that has been implemented > separately for each clock type. > > Implement that functionality in the sunxi-ng's common part making use of > the CCF rate liming capabilities, so that it is available for all clock > types. > > Suggested-by: Maxime Ripard <mripard@kernel.org> > Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> > Cc: stable@vger.kernel.org > --- > drivers/clk/sunxi-ng/ccu_common.c | 15 +++++++++++++++ > drivers/clk/sunxi-ng/ccu_common.h | 3 +++ > 2 files changed, 18 insertions(+) > > diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c > index 8babce55302f..2152063eee16 100644 > --- a/drivers/clk/sunxi-ng/ccu_common.c > +++ b/drivers/clk/sunxi-ng/ccu_common.c > @@ -44,6 +44,12 @@ bool ccu_is_better_rate(struct ccu_common *common, > unsigned long current_rate, > unsigned long best_rate) > { > + if (common->max_rate && current_rate > common->max_rate) > + return false; > + > + if (common->min_rate && current_rate < common->min_rate) > + return false; > + We should use clk_hw_get_rate_range() here, there might be some additional constraints to the rate range than the hardware ones (ie, calls to clk_set_rate_range()). > if (common->features & CCU_FEATURE_CLOSEST_RATE) > return abs(current_rate - target_rate) < abs(best_rate - target_rate); > > @@ -122,7 +128,10 @@ static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev, > > for (i = 0; i < desc->hw_clks->num ; i++) { > struct clk_hw *hw = desc->hw_clks->hws[i]; > + struct ccu_common *common = hw_to_ccu_common(hw); > const char *name; > + unsigned long min_rate = 0; > + unsigned long max_rate = ULONG_MAX; > > if (!hw) > continue; > @@ -136,6 +145,12 @@ static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev, > pr_err("Couldn't register clock %d - %s\n", i, name); > goto err_clk_unreg; > } > + > + if (common->min_rate) > + min_rate = common->min_rate; > + if (common->max_rate) > + max_rate = common->max_rate; max_rate should always be set to ULONG_MAX. I would drop the tests for both here, and warn if max_rate is set to 0. Maxime
diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c index 8babce55302f..2152063eee16 100644 --- a/drivers/clk/sunxi-ng/ccu_common.c +++ b/drivers/clk/sunxi-ng/ccu_common.c @@ -44,6 +44,12 @@ bool ccu_is_better_rate(struct ccu_common *common, unsigned long current_rate, unsigned long best_rate) { + if (common->max_rate && current_rate > common->max_rate) + return false; + + if (common->min_rate && current_rate < common->min_rate) + return false; + if (common->features & CCU_FEATURE_CLOSEST_RATE) return abs(current_rate - target_rate) < abs(best_rate - target_rate); @@ -122,7 +128,10 @@ static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev, for (i = 0; i < desc->hw_clks->num ; i++) { struct clk_hw *hw = desc->hw_clks->hws[i]; + struct ccu_common *common = hw_to_ccu_common(hw); const char *name; + unsigned long min_rate = 0; + unsigned long max_rate = ULONG_MAX; if (!hw) continue; @@ -136,6 +145,12 @@ static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev, pr_err("Couldn't register clock %d - %s\n", i, name); goto err_clk_unreg; } + + if (common->min_rate) + min_rate = common->min_rate; + if (common->max_rate) + max_rate = common->max_rate; + clk_hw_set_rate_range(hw, min_rate, max_rate); } ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h index 942a72c09437..329734f8cf42 100644 --- a/drivers/clk/sunxi-ng/ccu_common.h +++ b/drivers/clk/sunxi-ng/ccu_common.h @@ -31,6 +31,9 @@ struct ccu_common { u16 lock_reg; u32 prediv; + unsigned long min_rate; + unsigned long max_rate; + unsigned long features; spinlock_t *lock; struct clk_hw hw;
The Allwinner SoC's typically have an upper and lower limit for their clocks' rates. Up until now, support for that has been implemented separately for each clock type. Implement that functionality in the sunxi-ng's common part making use of the CCF rate liming capabilities, so that it is available for all clock types. Suggested-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Cc: stable@vger.kernel.org --- drivers/clk/sunxi-ng/ccu_common.c | 15 +++++++++++++++ drivers/clk/sunxi-ng/ccu_common.h | 3 +++ 2 files changed, 18 insertions(+)