| Message ID | 20240304090248.1247215-1-qiujingbao.dlmu@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: pwm: sophgo: add pwm support for CV1800 | expand |
On 04/03/2024 10:02, Jingbao Qiu wrote: > Implement the PWM driver for CV1800. > > Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> ... > + > + ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put, > + priv->clk); > + if (ret) { > + clk_rate_exclusive_put(priv->clk); > + return ret; Please test this path - you have double put. Best regards, Krzysztof
On Mon, Mar 4, 2024 at 6:15 PM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 04/03/2024 10:02, Jingbao Qiu wrote: > > Implement the PWM driver for CV1800. > > > > Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> > > ... > > > + > > + ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put, > > + priv->clk); > > + if (ret) { > > + clk_rate_exclusive_put(priv->clk); > > + return ret; > > Please test this path - you have double put. > Thank you for your reply. You're right. If the devm_add_action_or_reset() function fails to add an action, it will call the action. By the way, if I need to resend the patch, should I wait for the maintainer to review it, or should I immediately correct this error and resend it. Best regards, Jingbao Qiu
On 04/03/2024 14:40, Jingbao Qiu wrote: > On Mon, Mar 4, 2024 at 6:15 PM Krzysztof Kozlowski > <krzysztof.kozlowski@linaro.org> wrote: >> >> On 04/03/2024 10:02, Jingbao Qiu wrote: >>> Implement the PWM driver for CV1800. >>> >>> Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> >> >> ... >> >>> + >>> + ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put, >>> + priv->clk); >>> + if (ret) { >>> + clk_rate_exclusive_put(priv->clk); >>> + return ret; >> >> Please test this path - you have double put. >> > > Thank you for your reply. You're right. If the > devm_add_action_or_reset() function > fails to add an action, it will call the action. > > By the way, if I need to resend the patch, should I wait for the > maintainer to review it, or > should I immediately correct this error and resend it. I recommend one patchset per day. Best regards, Krzysztof
Hello, thanks for your patch. On Mon, Mar 04, 2024 at 05:02:48PM +0800, Jingbao Qiu wrote: > Implement the PWM driver for CV1800. > > Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> > --- > drivers/pwm/Kconfig | 10 ++ > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-cv1800.c | 314 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 325 insertions(+) > create mode 100644 drivers/pwm/pwm-cv1800.c > > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index 4b956d661755..455f07af94f7 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -186,6 +186,16 @@ config PWM_CROS_EC > PWM driver for exposing a PWM attached to the ChromeOS Embedded > Controller. > > +config PWM_CV1800 > + tristate "Sophgo CV1800 PWM driver" > + depends on ARCH_SOPHGO || COMPILE_TEST > + help > + Generic PWM framework driver for the Sophgo CV1800 series > + SoCs. > + > + To compile this driver as a module, build the dependecies > + as modules, this will be called pwm-cv1800. > + > config PWM_DWC_CORE > tristate > depends on HAS_IOMEM > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > index c5ec9e168ee7..6c3c4a07a316 100644 > --- a/drivers/pwm/Makefile > +++ b/drivers/pwm/Makefile > @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLK) += pwm-clk.o > obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o > obj-$(CONFIG_PWM_CRC) += pwm-crc.o > obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o > +obj-$(CONFIG_PWM_CV1800) += pwm-cv1800.o > obj-$(CONFIG_PWM_DWC_CORE) += pwm-dwc-core.o > obj-$(CONFIG_PWM_DWC) += pwm-dwc.o > obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o > diff --git a/drivers/pwm/pwm-cv1800.c b/drivers/pwm/pwm-cv1800.c > new file mode 100644 > index 000000000000..d5b31a2b7787 > --- /dev/null > +++ b/drivers/pwm/pwm-cv1800.c > @@ -0,0 +1,314 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * pwm-cv1800.c: PWM driver for Sophgo cv1800 Mentioning the filename in the file isn't very helpful. It's obvious information. > + * Author: Jingbao Qiu <qiujingbao.dlmu@gmail.com> > + * > + * Limitations: > + * - It output low when PWM channel disabled. > + * - This pwm device supports dynamic loading of PWM parameters. When PWMSTART > + * is written from 0 to 1, the register value (HLPERIODn, PERIODn) will be > + * temporarily stored inside the PWM. If you want to dynamically change the > + * waveform during PWM output, after writing the new value to HLPERIODn and > + * PERIODn, write 1 and then 0 to PWMUPDATE[n] to make the new value effective. > + * - Supports up to Rate/2 output, and the lowest is about Rate/(2^30-1). > + * - By setting HLPERIODn to 0, can produce 100% duty cycle. > + * - This hardware could support inverted polarity. By default, the value of the > + * POLARITY register is 0x0. This means that HLPERIOD represents the number > + * of low level beats. > + * - This hardware supports input mode and output mode, implemented through the > + * Output-Enable/OE register. However, this driver has not yet implemented > + * capture callback. > + */ > + > +#include <linux/clk.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/pwm.h> > +#include <linux/regmap.h> > + > +#define PWM_CV1800_HLPERIOD_BASE 0x00 > +#define PWM_CV1800_PERIOD_BASE 0x04 > +#define PWM_CV1800_POLARITY 0x40 > +#define PWM_CV1800_START 0x44 > +#define PWM_CV1800_DONE 0x48 > +#define PWM_CV1800_UPDATE 0x4c > +#define PWM_CV1800_OE 0xd0 > + > +#define PWM_CV1800_HLPERIOD(n) (PWM_CV1800_HLPERIOD_BASE + ((n) * 0x08)) > +#define PWM_CV1800_PERIOD(n) (PWM_CV1800_PERIOD_BASE + ((n) * 0x08)) > + > +#define PWM_CV1800_UPDATE_MASK(n) (BIT(0) << (n)) > +#define PWM_CV1800_OE_MASK(n) (BIT(0) << (n)) > +#define PWM_CV1800_START_MASK(n) (BIT(0) << (n)) > +#define PWM_CV1800_POLARITY_MASK(n) (BIT(0) << (n)) > + > +#define PWM_CV1800_OE_INPUT 0x00U > +#define PWM_CV1800_OE_OUTPUT(n) (BIT(0) << (n)) > +#define PWM_CV1800_MAXPERIOD (BIT(30) - 1) > +#define PWM_CV1800_MINPERIOD BIT(1) These are minimal and maximal values. I'd do #define PWM_CV1800_MAXPERIOD 0x3fffffff #define PWM_CV1800_MINPERIOD 2 > +#define PWM_CV1800_PERIOD_RESET BIT(1) > +#define PWM_CV1800_HLPERIOD_RESET BIT(0) > +#define PWM_CV1800_REG_DISABLE 0x00U > +#define PWM_CV1800_REG_ENABLE(n) (BIT(0) << (n)) > +#define PWM_CV1800_CHANNELS 4 > + > +struct cv1800_pwm { > + struct regmap *map; > + struct clk *clk; > + unsigned long clk_rate; > +}; > + > +static inline struct cv1800_pwm *to_cv1800_pwm_dev(struct pwm_chip *chip) > +{ > + return pwmchip_get_drvdata(chip); > +} > + > +static const struct regmap_config cv1800_pwm_regmap_config = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > +}; > + > +static int cv1800_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, > + bool enable) > +{ > + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); > + u32 pwm_enable; > + > + regmap_read(priv->map, PWM_CV1800_START, &pwm_enable); > + pwm_enable &= PWM_CV1800_START_MASK(pwm->hwpwm); > + > + /* > + * If the parameters are changed during runtime, Register needs > + * to be updated to take effect. > + */ > + if (pwm_enable && enable) { > + regmap_update_bits(priv->map, PWM_CV1800_UPDATE, > + PWM_CV1800_UPDATE_MASK(pwm->hwpwm), > + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); > + regmap_update_bits(priv->map, PWM_CV1800_UPDATE, > + PWM_CV1800_UPDATE_MASK(pwm->hwpwm), > + PWM_CV1800_REG_DISABLE); > + } else if (!pwm_enable && enable) { > + regmap_update_bits(priv->map, PWM_CV1800_START, > + PWM_CV1800_START_MASK(pwm->hwpwm), > + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); > + } else if (pwm_enable && !enable) { > + regmap_update_bits(priv->map, PWM_CV1800_START, > + PWM_CV1800_START_MASK(pwm->hwpwm), > + PWM_CV1800_REG_DISABLE); > + } > + > + return 0; > +} > + > +static void cv1800_pwm_set_polarity(struct pwm_chip *chip, > + struct pwm_device *pwm, > + enum pwm_polarity polarity) > +{ > + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); > + > + if (pwm->state.enabled) > + cv1800_pwm_enable(chip, pwm, !pwm->state.enabled); > + > + if (polarity == PWM_POLARITY_INVERSED) > + regmap_update_bits(priv->map, PWM_CV1800_POLARITY, > + PWM_CV1800_POLARITY_MASK(pwm->hwpwm), > + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); > + else > + regmap_update_bits(priv->map, PWM_CV1800_POLARITY, > + PWM_CV1800_POLARITY_MASK(pwm->hwpwm), > + PWM_CV1800_REG_DISABLE); Wouldn't it be more natural to make this read: if (polarity == PWM_POLARITY_INVERSED) regmap_update_bits(priv->map, PWM_CV1800_POLARITY, PWM_CV1800_POLARITY_MASK(pwm->hwpwm), PWM_CV1800_POLARITY_MASK(pwm->hwpwm)); else regmap_update_bits(priv->map, PWM_CV1800_POLARITY, PWM_CV1800_POLARITY_MASK(pwm->hwpwm), 0); or even: u32 polarity = 0; if (polarity == PWM_POLARITY_INVERSED) polarity = PWM_CV1800_POLARITY_MASK(pwm->hwpwm); regmap_update_bits(priv->map, PWM_CV1800_POLARITY, PWM_CV1800_POLARITY_MASK(pwm->hwpwm), polarity); ? > +} > + > +static void cv1800_pwm_set_oe(struct pwm_chip *chip, struct pwm_device *pwm, > + u32 mode) > +{ > + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); > + u32 state; > + > + regmap_read(priv->map, PWM_CV1800_OE, &state); > + state &= PWM_CV1800_OE_MASK(pwm->hwpwm); > + > + if (state == mode) > + return; > + > + cv1800_pwm_enable(chip, pwm, false); > + > + if (mode == PWM_CV1800_OE_INPUT) > + regmap_update_bits(priv->map, PWM_CV1800_OE, > + PWM_CV1800_OE_MASK(pwm->hwpwm), > + PWM_CV1800_REG_DISABLE); > + else if (mode == PWM_CV1800_OE_OUTPUT(pwm->hwpwm)) > + regmap_update_bits(priv->map, PWM_CV1800_OE, > + PWM_CV1800_OE_MASK(pwm->hwpwm), > + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); > +} What does this function do? A comment describing that would be good. I wonder about it being called unconditionally in .apply() below. > + > +static int cv1800_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > + const struct pwm_state *state) > +{ > + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); > + u32 period_val, hlperiod_val; > + u64 tem; > + > + cv1800_pwm_set_oe(chip, pwm, PWM_CV1800_OE_OUTPUT(pwm->hwpwm)); > + > + if (state->polarity != pwm->state.polarity) > + cv1800_pwm_set_polarity(chip, pwm, state->polarity); > + > + /* > + * This hardware use PERIOD and HLPERIOD registers to represent PWM waves. > + * > + * The meaning of PERIOD is how many clock cycles (from the clock source) > + * are used to represent PWM waves. > + * PERIOD = rate(MHz) / target(MHz) > + * PERIOD = period(ns) * rate(Hz) / NSEC_PER_SEC > + */ > + tem = mul_u64_u64_div_u64(state->period, priv->clk_rate, NSEC_PER_SEC); What does "tem" stand for? Maybe "ticks" is a better name? > + if (tem < PWM_CV1800_MINPERIOD) > + return -EINVAL; > + > + if (tem > PWM_CV1800_MAXPERIOD) > + tem = PWM_CV1800_MAXPERIOD; > + > + period_val = (u32)tem; > + > + /* > + * The meaning of HLPERIOD is the number of beats in the low or high level > + * of the PERIOD. When the value of the POLARITY register is 0, HLPERIOD > + * represents a low level. > + * HLPERIOD = period_val - rate(MHz) / duty(MHz) > + * HLPERIOD = period_val - duty(ns) * rate(Hz) / NSEC_PER_SEC So HLPERIOD defines the second part of each period, right? This isn't considered in .get_state(). > + */ > + tem = mul_u64_u64_div_u64(state->duty_cycle, priv->clk_rate, > + NSEC_PER_SEC); > + if (tem > period_val) > + return -EINVAL; if (tem > period_val) tem = period_val; > + hlperiod_val = period_val - (u32)tem; Wrong rounding I think. Did you test your driver with PWM_DEBUG enabled? > + regmap_write(priv->map, PWM_CV1800_PERIOD(pwm->hwpwm), period_val); > + regmap_write(priv->map, PWM_CV1800_HLPERIOD(pwm->hwpwm), hlperiod_val); > + > + cv1800_pwm_enable(chip, pwm, state->enabled); > + > + return 0; > +} > + > +static int cv1800_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, > + struct pwm_state *state) > +{ > + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); > + u32 period_val, hlperiod_val; > + u64 period_ns = 0; > + u64 duty_ns = 0; > + u32 enable = 0; > + u32 polarity = 0; > + > + regmap_read(priv->map, PWM_CV1800_PERIOD(pwm->hwpwm), &period_val); > + regmap_read(priv->map, PWM_CV1800_HLPERIOD(pwm->hwpwm), &hlperiod_val); > + > + if (period_val != PWM_CV1800_PERIOD_RESET || > + hlperiod_val != PWM_CV1800_HLPERIOD_RESET) { > + period_ns = DIV_ROUND_UP_ULL(period_val * NSEC_PER_SEC, > + priv->clk_rate); > + duty_ns = DIV_ROUND_UP_ULL(hlperiod_val * period_ns, period_val); > + > + regmap_read(priv->map, PWM_CV1800_START, &enable); > + enable &= PWM_CV1800_START_MASK(pwm->hwpwm); > + > + regmap_read(priv->map, PWM_CV1800_POLARITY, &polarity); > + polarity &= PWM_CV1800_POLARITY_MASK(pwm->hwpwm); > + } > + > + state->period = period_ns; > + state->duty_cycle = duty_ns; > + state->enabled = enable; > + state->polarity = polarity ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; > + > + return 0; > +} > + > +static const struct pwm_ops cv1800_pwm_ops = { > + .apply = cv1800_pwm_apply, > + .get_state = cv1800_pwm_get_state, > +}; > + > +static void devm_clk_rate_exclusive_put(void *data) > +{ > + struct clk *clk = data; > + > + clk_rate_exclusive_put(clk); > +} > + > +static int cv1800_pwm_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct cv1800_pwm *priv; > + struct pwm_chip *chip; > + void __iomem *base; > + int ret; > + > + chip = devm_pwmchip_alloc(dev, PWM_CV1800_CHANNELS, sizeof(*priv)); > + if (!chip) > + return PTR_ERR(chip); > + priv = to_cv1800_pwm_dev(chip); > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + priv->map = devm_regmap_init_mmio(&pdev->dev, base, > + &cv1800_pwm_regmap_config); > + if (IS_ERR(priv->map)) > + return PTR_ERR(priv->map); > + > + priv->clk = devm_clk_get_enabled(&pdev->dev, NULL); > + if (IS_ERR(priv->clk)) > + return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), > + "clk not found\n"); > + > + ret = clk_rate_exclusive_get(priv->clk); There is a devm_clk_rate_exclusive_get() in next. Please make use of it. (See commit b0cde62e4c54) > + if (ret) > + return dev_err_probe(&pdev->dev, ret, > + "failed to get exclusive rate\n"); > + > + ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put, > + priv->clk); > + if (ret) { > + clk_rate_exclusive_put(priv->clk); > + return ret; > + } > + > + priv->clk_rate = clk_get_rate(priv->clk); > + if (!priv->clk_rate) > + return dev_err_probe(&pdev->dev, -EINVAL, > + "Invalid clock rate: %lu\n", > + priv->clk_rate); > + > + chip->ops = &cv1800_pwm_ops; > + > + return devm_pwmchip_add(dev, chip); Error message if devm_pwmchip_add() fails, please. > +} > + > +static const struct of_device_id cv1800_pwm_dt_ids[] = { > + { .compatible = "sophgo,cv1800-pwm" }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, cv1800_pwm_dt_ids); > + > +static struct platform_driver cv1800_pwm_driver = { > + .probe = cv1800_pwm_probe, > + .driver = { > + .name = "cv1800-pwm", > + .of_match_table = cv1800_pwm_dt_ids, > + }, > +}; > +module_platform_driver(cv1800_pwm_driver); > + > +MODULE_AUTHOR("Jingbao Qiu"); > +MODULE_DESCRIPTION("Sophgo cv1800 PWM Driver"); > +MODULE_LICENSE("GPL"); Best regards Uwe
On Mon, Mar 4, 2024 at 11:02 PM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 04/03/2024 14:40, Jingbao Qiu wrote: > > On Mon, Mar 4, 2024 at 6:15 PM Krzysztof Kozlowski > > <krzysztof.kozlowski@linaro.org> wrote: > >> > >> On 04/03/2024 10:02, Jingbao Qiu wrote: > >>> Implement the PWM driver for CV1800. > >>> > >>> Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> > >> > >> ... > >> > >>> + > >>> + ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put, > >>> + priv->clk); > >>> + if (ret) { > >>> + clk_rate_exclusive_put(priv->clk); > >>> + return ret; > >> > >> Please test this path - you have double put. > >> > > > > Thank you for your reply. You're right. If the > > devm_add_action_or_reset() function > > fails to add an action, it will call the action. > > > > By the way, if I need to resend the patch, should I wait for the > > maintainer to review it, or > > should I immediately correct this error and resend it. > > I recommend one patchset per day. > Thank you for your suggestion. Best regards, Jingbao Qiu
Hi Uwe, On Mon, Mar 4, 2024 at 11:37 PM Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote: > > Hello, > > thanks for your patch. > > On Mon, Mar 04, 2024 at 05:02:48PM +0800, Jingbao Qiu wrote: > > Implement the PWM driver for CV1800. > > > > Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> > > --- > > drivers/pwm/Kconfig | 10 ++ > > drivers/pwm/Makefile | 1 + > > drivers/pwm/pwm-cv1800.c | 314 +++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 325 insertions(+) > > create mode 100644 drivers/pwm/pwm-cv1800.c > > > > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > > index 4b956d661755..455f07af94f7 100644 > > --- a/drivers/pwm/Kconfig > > +++ b/drivers/pwm/Kconfig > > @@ -186,6 +186,16 @@ config PWM_CROS_EC > > PWM driver for exposing a PWM attached to the ChromeOS Embedded > > Controller. > > > > +config PWM_CV1800 > > + tristate "Sophgo CV1800 PWM driver" > > + depends on ARCH_SOPHGO || COMPILE_TEST > > + help > > + Generic PWM framework driver for the Sophgo CV1800 series > > + SoCs. > > + > > + To compile this driver as a module, build the dependecies > > + as modules, this will be called pwm-cv1800. > > + > > config PWM_DWC_CORE > > tristate > > depends on HAS_IOMEM > > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > > index c5ec9e168ee7..6c3c4a07a316 100644 > > --- a/drivers/pwm/Makefile > > +++ b/drivers/pwm/Makefile > > @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLK) += pwm-clk.o > > obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o > > obj-$(CONFIG_PWM_CRC) += pwm-crc.o > > obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o > > +obj-$(CONFIG_PWM_CV1800) += pwm-cv1800.o > > obj-$(CONFIG_PWM_DWC_CORE) += pwm-dwc-core.o > > obj-$(CONFIG_PWM_DWC) += pwm-dwc.o > > obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o > > diff --git a/drivers/pwm/pwm-cv1800.c b/drivers/pwm/pwm-cv1800.c > > new file mode 100644 > > index 000000000000..d5b31a2b7787 > > --- /dev/null > > +++ b/drivers/pwm/pwm-cv1800.c > > @@ -0,0 +1,314 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * pwm-cv1800.c: PWM driver for Sophgo cv1800 > > Mentioning the filename in the file isn't very helpful. It's obvious > information. I will drop this line. > > > + * Author: Jingbao Qiu <qiujingbao.dlmu@gmail.com> > > + * > > + * Limitations: > > + * - It output low when PWM channel disabled. > > + * - This pwm device supports dynamic loading of PWM parameters. When PWMSTART > > + * is written from 0 to 1, the register value (HLPERIODn, PERIODn) will be > > + * temporarily stored inside the PWM. If you want to dynamically change the > > + * waveform during PWM output, after writing the new value to HLPERIODn and > > + * PERIODn, write 1 and then 0 to PWMUPDATE[n] to make the new value effective. > > + * - Supports up to Rate/2 output, and the lowest is about Rate/(2^30-1). > > + * - By setting HLPERIODn to 0, can produce 100% duty cycle. > > + * - This hardware could support inverted polarity. By default, the value of the > > + * POLARITY register is 0x0. This means that HLPERIOD represents the number > > + * of low level beats. > > + * - This hardware supports input mode and output mode, implemented through the > > + * Output-Enable/OE register. However, this driver has not yet implemented > > + * capture callback. > > + */ > > + > > +#include <linux/clk.h> > > +#include <linux/kernel.h> > > +#include <linux/module.h> > > +#include <linux/of.h> > > +#include <linux/platform_device.h> > > +#include <linux/pwm.h> > > +#include <linux/regmap.h> > > + > > +#define PWM_CV1800_HLPERIOD_BASE 0x00 > > +#define PWM_CV1800_PERIOD_BASE 0x04 > > +#define PWM_CV1800_POLARITY 0x40 > > +#define PWM_CV1800_START 0x44 > > +#define PWM_CV1800_DONE 0x48 > > +#define PWM_CV1800_UPDATE 0x4c > > +#define PWM_CV1800_OE 0xd0 > > + > > +#define PWM_CV1800_HLPERIOD(n) (PWM_CV1800_HLPERIOD_BASE + ((n) * 0x08)) > > +#define PWM_CV1800_PERIOD(n) (PWM_CV1800_PERIOD_BASE + ((n) * 0x08)) > > + > > +#define PWM_CV1800_UPDATE_MASK(n) (BIT(0) << (n)) > > +#define PWM_CV1800_OE_MASK(n) (BIT(0) << (n)) > > +#define PWM_CV1800_START_MASK(n) (BIT(0) << (n)) > > +#define PWM_CV1800_POLARITY_MASK(n) (BIT(0) << (n)) > > + > > +#define PWM_CV1800_OE_INPUT 0x00U > > +#define PWM_CV1800_OE_OUTPUT(n) (BIT(0) << (n)) > > +#define PWM_CV1800_MAXPERIOD (BIT(30) - 1) > > +#define PWM_CV1800_MINPERIOD BIT(1) > > These are minimal and maximal values. I'd do > > #define PWM_CV1800_MAXPERIOD 0x3fffffff > #define PWM_CV1800_MINPERIOD 2 > I will fix it. > > +#define PWM_CV1800_PERIOD_RESET BIT(1) > > +#define PWM_CV1800_HLPERIOD_RESET BIT(0) > > +#define PWM_CV1800_REG_DISABLE 0x00U > > +#define PWM_CV1800_REG_ENABLE(n) (BIT(0) << (n)) > > +#define PWM_CV1800_CHANNELS 4 > > + > > +struct cv1800_pwm { > > + struct regmap *map; > > + struct clk *clk; > > + unsigned long clk_rate; > > +}; > > + > > +static inline struct cv1800_pwm *to_cv1800_pwm_dev(struct pwm_chip *chip) > > +{ > > + return pwmchip_get_drvdata(chip); > > +} > > + > > +static const struct regmap_config cv1800_pwm_regmap_config = { > > + .reg_bits = 32, > > + .val_bits = 32, > > + .reg_stride = 4, > > +}; > > + > > +static int cv1800_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, > > + bool enable) > > +{ > > + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); > > + u32 pwm_enable; > > + > > + regmap_read(priv->map, PWM_CV1800_START, &pwm_enable); > > + pwm_enable &= PWM_CV1800_START_MASK(pwm->hwpwm); > > + > > + /* > > + * If the parameters are changed during runtime, Register needs > > + * to be updated to take effect. > > + */ > > + if (pwm_enable && enable) { > > + regmap_update_bits(priv->map, PWM_CV1800_UPDATE, > > + PWM_CV1800_UPDATE_MASK(pwm->hwpwm), > > + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); > > + regmap_update_bits(priv->map, PWM_CV1800_UPDATE, > > + PWM_CV1800_UPDATE_MASK(pwm->hwpwm), > > + PWM_CV1800_REG_DISABLE); > > + } else if (!pwm_enable && enable) { > > + regmap_update_bits(priv->map, PWM_CV1800_START, > > + PWM_CV1800_START_MASK(pwm->hwpwm), > > + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); > > + } else if (pwm_enable && !enable) { > > + regmap_update_bits(priv->map, PWM_CV1800_START, > > + PWM_CV1800_START_MASK(pwm->hwpwm), > > + PWM_CV1800_REG_DISABLE); > > + } > > + > > + return 0; > > +} > > + > > +static void cv1800_pwm_set_polarity(struct pwm_chip *chip, > > + struct pwm_device *pwm, > > + enum pwm_polarity polarity) > > +{ > > + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); > > + > > + if (pwm->state.enabled) > > + cv1800_pwm_enable(chip, pwm, !pwm->state.enabled); > > + > > + if (polarity == PWM_POLARITY_INVERSED) > > + regmap_update_bits(priv->map, PWM_CV1800_POLARITY, > > + PWM_CV1800_POLARITY_MASK(pwm->hwpwm), > > + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); > > + else > > + regmap_update_bits(priv->map, PWM_CV1800_POLARITY, > > + PWM_CV1800_POLARITY_MASK(pwm->hwpwm), > > + PWM_CV1800_REG_DISABLE); > > Wouldn't it be more natural to make this read: > > if (polarity == PWM_POLARITY_INVERSED) > regmap_update_bits(priv->map, PWM_CV1800_POLARITY, > PWM_CV1800_POLARITY_MASK(pwm->hwpwm), > PWM_CV1800_POLARITY_MASK(pwm->hwpwm)); > else > regmap_update_bits(priv->map, PWM_CV1800_POLARITY, > PWM_CV1800_POLARITY_MASK(pwm->hwpwm), > 0); > > or even: > > u32 polarity = 0; > > if (polarity == PWM_POLARITY_INVERSED) > polarity = PWM_CV1800_POLARITY_MASK(pwm->hwpwm); > > regmap_update_bits(priv->map, PWM_CV1800_POLARITY, > PWM_CV1800_POLARITY_MASK(pwm->hwpwm), > polarity); > > ? > Good idea. My code looks so bloated. I will fix it. > > +} > > + > > +static void cv1800_pwm_set_oe(struct pwm_chip *chip, struct pwm_device *pwm, > > + u32 mode) > > +{ > > + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); > > + u32 state; > > + > > + regmap_read(priv->map, PWM_CV1800_OE, &state); > > + state &= PWM_CV1800_OE_MASK(pwm->hwpwm); > > + > > + if (state == mode) > > + return; > > + > > + cv1800_pwm_enable(chip, pwm, false); > > + > > + if (mode == PWM_CV1800_OE_INPUT) > > + regmap_update_bits(priv->map, PWM_CV1800_OE, > > + PWM_CV1800_OE_MASK(pwm->hwpwm), > > + PWM_CV1800_REG_DISABLE); > > + else if (mode == PWM_CV1800_OE_OUTPUT(pwm->hwpwm)) > > + regmap_update_bits(priv->map, PWM_CV1800_OE, > > + PWM_CV1800_OE_MASK(pwm->hwpwm), > > + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); > > +} > > What does this function do? A comment describing that would be good. I > wonder about it being called unconditionally in .apply() below. I will add a comment for this function. > > > + > > +static int cv1800_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > + const struct pwm_state *state) > > +{ > > + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); > > + u32 period_val, hlperiod_val; > > + u64 tem; > > + > > + cv1800_pwm_set_oe(chip, pwm, PWM_CV1800_OE_OUTPUT(pwm->hwpwm)); > > + > > + if (state->polarity != pwm->state.polarity) > > + cv1800_pwm_set_polarity(chip, pwm, state->polarity); > > + > > + /* > > + * This hardware use PERIOD and HLPERIOD registers to represent PWM waves. > > + * > > + * The meaning of PERIOD is how many clock cycles (from the clock source) > > + * are used to represent PWM waves. > > + * PERIOD = rate(MHz) / target(MHz) > > + * PERIOD = period(ns) * rate(Hz) / NSEC_PER_SEC > > + */ > > + tem = mul_u64_u64_div_u64(state->period, priv->clk_rate, NSEC_PER_SEC); > > What does "tem" stand for? Maybe "ticks" is a better name? "ticks" looks better. I will use it. > > > + if (tem < PWM_CV1800_MINPERIOD) > > + return -EINVAL; > > + > > + if (tem > PWM_CV1800_MAXPERIOD) > > + tem = PWM_CV1800_MAXPERIOD; > > + > > + period_val = (u32)tem; > > + > > + /* > > + * The meaning of HLPERIOD is the number of beats in the low or high level > > + * of the PERIOD. When the value of the POLARITY register is 0, HLPERIOD > > + * represents a low level. > > + * HLPERIOD = period_val - rate(MHz) / duty(MHz) > > + * HLPERIOD = period_val - duty(ns) * rate(Hz) / NSEC_PER_SEC > > So HLPERIOD defines the second part of each period, right? This isn't > considered in .get_state(). I am so sorry about this. I made a mess of the duty cycle. According to the PWM_DEBUG, it can be inferred that configure the biggest duty_cycle not bigger than the requested value, so in .apply duty_cycle should round down and in .get_state duty_cycle should round up. However, when the polarity is normal, This hardware requires a low-level beat count. So the corrected code is as follows. in .apply() ticks = mul_u64_u64_div_u64(state->duty_cycle , priv->clk_rate,NSEC_PER_SEC); ... hlperiod_val =period_val- (u32)ticks; in .get_state() u32 hlperiod_val=0; period_ns = DIV_ROUND_UP_ULL(period_val * NSEC_PER_SEC,priv->clk_rate); duty_ns = DIV_ROUND_UP_ULL(hlperiod_val * period_ns, period_val); hlperiod_val = period_ns - duty_ns; I tested this code with PWM_DEBUG. no warning output. What do you think about this? > > > + */ > > + tem = mul_u64_u64_div_u64(state->duty_cycle, priv->clk_rate, > > + NSEC_PER_SEC); > > + if (tem > period_val) > > + return -EINVAL; > > if (tem > period_val) > tem = period_val; > > > + hlperiod_val = period_val - (u32)tem; > > Wrong rounding I think. Did you test your driver with PWM_DEBUG enabled? ditto. > > > + regmap_write(priv->map, PWM_CV1800_PERIOD(pwm->hwpwm), period_val); > > + regmap_write(priv->map, PWM_CV1800_HLPERIOD(pwm->hwpwm), hlperiod_val); > > + > > + cv1800_pwm_enable(chip, pwm, state->enabled); > > + > > + return 0; > > +} > > + > > +static int cv1800_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, > > + struct pwm_state *state) > > +{ > > + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); > > + u32 period_val, hlperiod_val; > > + u64 period_ns = 0; > > + u64 duty_ns = 0; > > + u32 enable = 0; > > + u32 polarity = 0; > > + > > + regmap_read(priv->map, PWM_CV1800_PERIOD(pwm->hwpwm), &period_val); > > + regmap_read(priv->map, PWM_CV1800_HLPERIOD(pwm->hwpwm), &hlperiod_val); > > + > > + if (period_val != PWM_CV1800_PERIOD_RESET || > > + hlperiod_val != PWM_CV1800_HLPERIOD_RESET) { > > + period_ns = DIV_ROUND_UP_ULL(period_val * NSEC_PER_SEC, > > + priv->clk_rate); > > + duty_ns = DIV_ROUND_UP_ULL(hlperiod_val * period_ns, period_val); > > + > > + regmap_read(priv->map, PWM_CV1800_START, &enable); > > + enable &= PWM_CV1800_START_MASK(pwm->hwpwm); > > + > > + regmap_read(priv->map, PWM_CV1800_POLARITY, &polarity); > > + polarity &= PWM_CV1800_POLARITY_MASK(pwm->hwpwm); > > + } > > + > > + state->period = period_ns; > > + state->duty_cycle = duty_ns; > > + state->enabled = enable; > > + state->polarity = polarity ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; > > + > > + return 0; > > +} > > + > > +static const struct pwm_ops cv1800_pwm_ops = { > > + .apply = cv1800_pwm_apply, > > + .get_state = cv1800_pwm_get_state, > > +}; > > + > > +static void devm_clk_rate_exclusive_put(void *data) > > +{ > > + struct clk *clk = data; > > + > > + clk_rate_exclusive_put(clk); > > +} > > + > > +static int cv1800_pwm_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + struct cv1800_pwm *priv; > > + struct pwm_chip *chip; > > + void __iomem *base; > > + int ret; > > + > > + chip = devm_pwmchip_alloc(dev, PWM_CV1800_CHANNELS, sizeof(*priv)); > > + if (!chip) > > + return PTR_ERR(chip); > > + priv = to_cv1800_pwm_dev(chip); > > + > > + base = devm_platform_ioremap_resource(pdev, 0); > > + if (IS_ERR(base)) > > + return PTR_ERR(base); > > + > > + priv->map = devm_regmap_init_mmio(&pdev->dev, base, > > + &cv1800_pwm_regmap_config); > > + if (IS_ERR(priv->map)) > > + return PTR_ERR(priv->map); > > + > > + priv->clk = devm_clk_get_enabled(&pdev->dev, NULL); > > + if (IS_ERR(priv->clk)) > > + return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), > > + "clk not found\n"); > > + > > + ret = clk_rate_exclusive_get(priv->clk); > > There is a devm_clk_rate_exclusive_get() in next. Please make use of it. > (See commit b0cde62e4c54) I will use this branch. > > > + if (ret) > > + return dev_err_probe(&pdev->dev, ret, > > + "failed to get exclusive rate\n");> > + > > + ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put, > > + priv->clk); > > + if (ret) { > > + clk_rate_exclusive_put(priv->clk); > > + return ret; > > + } > > + > > + priv->clk_rate = clk_get_rate(priv->clk); > > + if (!priv->clk_rate) > > + return dev_err_probe(&pdev->dev, -EINVAL, > > + "Invalid clock rate: %lu\n", > > + priv->clk_rate); > > + > > + chip->ops = &cv1800_pwm_ops; > > + > > + return devm_pwmchip_add(dev, chip); > > Error message if devm_pwmchip_add() fails, please. I will fix it. Thank you for your reply. Best regards Jingbao Qiu
Hi Uwe, Gentle ping, I'm sorry for wasting your time, and I look forward to your feedback. > > > + if (tem < PWM_CV1800_MINPERIOD) > > > + return -EINVAL; > > > + > > > + if (tem > PWM_CV1800_MAXPERIOD) > > > + tem = PWM_CV1800_MAXPERIOD; > > > + > > > + period_val = (u32)tem; > > > + > > > + /* > > > + * The meaning of HLPERIOD is the number of beats in the low or high level > > > + * of the PERIOD. When the value of the POLARITY register is 0, HLPERIOD > > > + * represents a low level. > > > + * HLPERIOD = period_val - rate(MHz) / duty(MHz) > > > + * HLPERIOD = period_val - duty(ns) * rate(Hz) / NSEC_PER_SEC > > > > So HLPERIOD defines the second part of each period, right? This isn't > > considered in .get_state(). > > I am so sorry about this. I made a mess of the duty cycle. > According to the PWM_DEBUG, it can be inferred that configure the > biggest duty_cycle not > bigger than the requested value, so in .apply duty_cycle should round down and > in .get_state duty_cycle should round up. However, when the polarity is normal, > This hardware requires a low-level beat count. So the corrected code > is as follows. > > in .apply() > > ticks = mul_u64_u64_div_u64(state->duty_cycle , priv->clk_rate,NSEC_PER_SEC); > ... > hlperiod_val =period_val- (u32)ticks; > > in .get_state() > > u32 hlperiod_val=0; > > period_ns = DIV_ROUND_UP_ULL(period_val * NSEC_PER_SEC,priv->clk_rate); > duty_ns = DIV_ROUND_UP_ULL(hlperiod_val * period_ns, period_val); > hlperiod_val = period_ns - duty_ns; > > I tested this code with PWM_DEBUG. no warning output. What do you > think about this? > > in .apply() ticks = mul_u64_u64_div_u64(state->duty_cycle, priv->clk_rate, NSEC_PER_SEC); if (ticks > period_val) ticks = period_val; hlperiod_val = period_val - (u32)ticks; ... regmap_write(priv->map, PWM_CV1800_HLPERIOD(pwm->hwpwm), hlperiod_val); in .get_state() u64 hlperiod_ns = 0; regmap_read(priv->map, PWM_CV1800_HLPERIOD(pwm->hwpwm), &hlperiod_val); ... period_ns = DIV_ROUND_UP_ULL(period_val * NSEC_PER_SEC, priv->clk_rate); hlperiod_ns = DIV_ROUND_UP_ULL(hlperiod_val * NSEC_PER_SEC, priv->clk_rate); duty_ns = period_ns - hlperiod_ns; I tested this code with PWM_DEBUG. no warning output. > > > > > + */ > > > + tem = mul_u64_u64_div_u64(state->duty_cycle, priv->clk_rate, > > > + NSEC_PER_SEC); > > > + if (tem > period_val) > > > + return -EINVAL; > > > > if (tem > period_val) > > tem = period_val; > > > > > + hlperiod_val = period_val - (u32)tem; > > > > Wrong rounding I think. Did you test your driver with PWM_DEBUG enabled? > > ditto. > Best regards Jingbao Qiu
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 4b956d661755..455f07af94f7 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -186,6 +186,16 @@ config PWM_CROS_EC PWM driver for exposing a PWM attached to the ChromeOS Embedded Controller. +config PWM_CV1800 + tristate "Sophgo CV1800 PWM driver" + depends on ARCH_SOPHGO || COMPILE_TEST + help + Generic PWM framework driver for the Sophgo CV1800 series + SoCs. + + To compile this driver as a module, build the dependecies + as modules, this will be called pwm-cv1800. + config PWM_DWC_CORE tristate depends on HAS_IOMEM diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c5ec9e168ee7..6c3c4a07a316 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLK) += pwm-clk.o obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o obj-$(CONFIG_PWM_CRC) += pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o +obj-$(CONFIG_PWM_CV1800) += pwm-cv1800.o obj-$(CONFIG_PWM_DWC_CORE) += pwm-dwc-core.o obj-$(CONFIG_PWM_DWC) += pwm-dwc.o obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o diff --git a/drivers/pwm/pwm-cv1800.c b/drivers/pwm/pwm-cv1800.c new file mode 100644 index 000000000000..d5b31a2b7787 --- /dev/null +++ b/drivers/pwm/pwm-cv1800.c @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * pwm-cv1800.c: PWM driver for Sophgo cv1800 + * + * Author: Jingbao Qiu <qiujingbao.dlmu@gmail.com> + * + * Limitations: + * - It output low when PWM channel disabled. + * - This pwm device supports dynamic loading of PWM parameters. When PWMSTART + * is written from 0 to 1, the register value (HLPERIODn, PERIODn) will be + * temporarily stored inside the PWM. If you want to dynamically change the + * waveform during PWM output, after writing the new value to HLPERIODn and + * PERIODn, write 1 and then 0 to PWMUPDATE[n] to make the new value effective. + * - Supports up to Rate/2 output, and the lowest is about Rate/(2^30-1). + * - By setting HLPERIODn to 0, can produce 100% duty cycle. + * - This hardware could support inverted polarity. By default, the value of the + * POLARITY register is 0x0. This means that HLPERIOD represents the number + * of low level beats. + * - This hardware supports input mode and output mode, implemented through the + * Output-Enable/OE register. However, this driver has not yet implemented + * capture callback. + */ + +#include <linux/clk.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/regmap.h> + +#define PWM_CV1800_HLPERIOD_BASE 0x00 +#define PWM_CV1800_PERIOD_BASE 0x04 +#define PWM_CV1800_POLARITY 0x40 +#define PWM_CV1800_START 0x44 +#define PWM_CV1800_DONE 0x48 +#define PWM_CV1800_UPDATE 0x4c +#define PWM_CV1800_OE 0xd0 + +#define PWM_CV1800_HLPERIOD(n) (PWM_CV1800_HLPERIOD_BASE + ((n) * 0x08)) +#define PWM_CV1800_PERIOD(n) (PWM_CV1800_PERIOD_BASE + ((n) * 0x08)) + +#define PWM_CV1800_UPDATE_MASK(n) (BIT(0) << (n)) +#define PWM_CV1800_OE_MASK(n) (BIT(0) << (n)) +#define PWM_CV1800_START_MASK(n) (BIT(0) << (n)) +#define PWM_CV1800_POLARITY_MASK(n) (BIT(0) << (n)) + +#define PWM_CV1800_OE_INPUT 0x00U +#define PWM_CV1800_OE_OUTPUT(n) (BIT(0) << (n)) +#define PWM_CV1800_MAXPERIOD (BIT(30) - 1) +#define PWM_CV1800_MINPERIOD BIT(1) +#define PWM_CV1800_PERIOD_RESET BIT(1) +#define PWM_CV1800_HLPERIOD_RESET BIT(0) +#define PWM_CV1800_REG_DISABLE 0x00U +#define PWM_CV1800_REG_ENABLE(n) (BIT(0) << (n)) +#define PWM_CV1800_CHANNELS 4 + +struct cv1800_pwm { + struct regmap *map; + struct clk *clk; + unsigned long clk_rate; +}; + +static inline struct cv1800_pwm *to_cv1800_pwm_dev(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static const struct regmap_config cv1800_pwm_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int cv1800_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, + bool enable) +{ + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); + u32 pwm_enable; + + regmap_read(priv->map, PWM_CV1800_START, &pwm_enable); + pwm_enable &= PWM_CV1800_START_MASK(pwm->hwpwm); + + /* + * If the parameters are changed during runtime, Register needs + * to be updated to take effect. + */ + if (pwm_enable && enable) { + regmap_update_bits(priv->map, PWM_CV1800_UPDATE, + PWM_CV1800_UPDATE_MASK(pwm->hwpwm), + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); + regmap_update_bits(priv->map, PWM_CV1800_UPDATE, + PWM_CV1800_UPDATE_MASK(pwm->hwpwm), + PWM_CV1800_REG_DISABLE); + } else if (!pwm_enable && enable) { + regmap_update_bits(priv->map, PWM_CV1800_START, + PWM_CV1800_START_MASK(pwm->hwpwm), + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); + } else if (pwm_enable && !enable) { + regmap_update_bits(priv->map, PWM_CV1800_START, + PWM_CV1800_START_MASK(pwm->hwpwm), + PWM_CV1800_REG_DISABLE); + } + + return 0; +} + +static void cv1800_pwm_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); + + if (pwm->state.enabled) + cv1800_pwm_enable(chip, pwm, !pwm->state.enabled); + + if (polarity == PWM_POLARITY_INVERSED) + regmap_update_bits(priv->map, PWM_CV1800_POLARITY, + PWM_CV1800_POLARITY_MASK(pwm->hwpwm), + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); + else + regmap_update_bits(priv->map, PWM_CV1800_POLARITY, + PWM_CV1800_POLARITY_MASK(pwm->hwpwm), + PWM_CV1800_REG_DISABLE); +} + +static void cv1800_pwm_set_oe(struct pwm_chip *chip, struct pwm_device *pwm, + u32 mode) +{ + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); + u32 state; + + regmap_read(priv->map, PWM_CV1800_OE, &state); + state &= PWM_CV1800_OE_MASK(pwm->hwpwm); + + if (state == mode) + return; + + cv1800_pwm_enable(chip, pwm, false); + + if (mode == PWM_CV1800_OE_INPUT) + regmap_update_bits(priv->map, PWM_CV1800_OE, + PWM_CV1800_OE_MASK(pwm->hwpwm), + PWM_CV1800_REG_DISABLE); + else if (mode == PWM_CV1800_OE_OUTPUT(pwm->hwpwm)) + regmap_update_bits(priv->map, PWM_CV1800_OE, + PWM_CV1800_OE_MASK(pwm->hwpwm), + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); +} + +static int cv1800_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); + u32 period_val, hlperiod_val; + u64 tem; + + cv1800_pwm_set_oe(chip, pwm, PWM_CV1800_OE_OUTPUT(pwm->hwpwm)); + + if (state->polarity != pwm->state.polarity) + cv1800_pwm_set_polarity(chip, pwm, state->polarity); + + /* + * This hardware use PERIOD and HLPERIOD registers to represent PWM waves. + * + * The meaning of PERIOD is how many clock cycles (from the clock source) + * are used to represent PWM waves. + * PERIOD = rate(MHz) / target(MHz) + * PERIOD = period(ns) * rate(Hz) / NSEC_PER_SEC + */ + tem = mul_u64_u64_div_u64(state->period, priv->clk_rate, NSEC_PER_SEC); + if (tem < PWM_CV1800_MINPERIOD) + return -EINVAL; + + if (tem > PWM_CV1800_MAXPERIOD) + tem = PWM_CV1800_MAXPERIOD; + + period_val = (u32)tem; + + /* + * The meaning of HLPERIOD is the number of beats in the low or high level + * of the PERIOD. When the value of the POLARITY register is 0, HLPERIOD + * represents a low level. + * HLPERIOD = period_val - rate(MHz) / duty(MHz) + * HLPERIOD = period_val - duty(ns) * rate(Hz) / NSEC_PER_SEC + */ + tem = mul_u64_u64_div_u64(state->duty_cycle, priv->clk_rate, + NSEC_PER_SEC); + if (tem > period_val) + return -EINVAL; + hlperiod_val = period_val - (u32)tem; + + regmap_write(priv->map, PWM_CV1800_PERIOD(pwm->hwpwm), period_val); + regmap_write(priv->map, PWM_CV1800_HLPERIOD(pwm->hwpwm), hlperiod_val); + + cv1800_pwm_enable(chip, pwm, state->enabled); + + return 0; +} + +static int cv1800_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct cv1800_pwm *priv = to_cv1800_pwm_dev(chip); + u32 period_val, hlperiod_val; + u64 period_ns = 0; + u64 duty_ns = 0; + u32 enable = 0; + u32 polarity = 0; + + regmap_read(priv->map, PWM_CV1800_PERIOD(pwm->hwpwm), &period_val); + regmap_read(priv->map, PWM_CV1800_HLPERIOD(pwm->hwpwm), &hlperiod_val); + + if (period_val != PWM_CV1800_PERIOD_RESET || + hlperiod_val != PWM_CV1800_HLPERIOD_RESET) { + period_ns = DIV_ROUND_UP_ULL(period_val * NSEC_PER_SEC, + priv->clk_rate); + duty_ns = DIV_ROUND_UP_ULL(hlperiod_val * period_ns, period_val); + + regmap_read(priv->map, PWM_CV1800_START, &enable); + enable &= PWM_CV1800_START_MASK(pwm->hwpwm); + + regmap_read(priv->map, PWM_CV1800_POLARITY, &polarity); + polarity &= PWM_CV1800_POLARITY_MASK(pwm->hwpwm); + } + + state->period = period_ns; + state->duty_cycle = duty_ns; + state->enabled = enable; + state->polarity = polarity ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; + + return 0; +} + +static const struct pwm_ops cv1800_pwm_ops = { + .apply = cv1800_pwm_apply, + .get_state = cv1800_pwm_get_state, +}; + +static void devm_clk_rate_exclusive_put(void *data) +{ + struct clk *clk = data; + + clk_rate_exclusive_put(clk); +} + +static int cv1800_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct cv1800_pwm *priv; + struct pwm_chip *chip; + void __iomem *base; + int ret; + + chip = devm_pwmchip_alloc(dev, PWM_CV1800_CHANNELS, sizeof(*priv)); + if (!chip) + return PTR_ERR(chip); + priv = to_cv1800_pwm_dev(chip); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->map = devm_regmap_init_mmio(&pdev->dev, base, + &cv1800_pwm_regmap_config); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + priv->clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), + "clk not found\n"); + + ret = clk_rate_exclusive_get(priv->clk); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to get exclusive rate\n"); + + ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put, + priv->clk); + if (ret) { + clk_rate_exclusive_put(priv->clk); + return ret; + } + + priv->clk_rate = clk_get_rate(priv->clk); + if (!priv->clk_rate) + return dev_err_probe(&pdev->dev, -EINVAL, + "Invalid clock rate: %lu\n", + priv->clk_rate); + + chip->ops = &cv1800_pwm_ops; + + return devm_pwmchip_add(dev, chip); +} + +static const struct of_device_id cv1800_pwm_dt_ids[] = { + { .compatible = "sophgo,cv1800-pwm" }, + {}, +}; +MODULE_DEVICE_TABLE(of, cv1800_pwm_dt_ids); + +static struct platform_driver cv1800_pwm_driver = { + .probe = cv1800_pwm_probe, + .driver = { + .name = "cv1800-pwm", + .of_match_table = cv1800_pwm_dt_ids, + }, +}; +module_platform_driver(cv1800_pwm_driver); + +MODULE_AUTHOR("Jingbao Qiu"); +MODULE_DESCRIPTION("Sophgo cv1800 PWM Driver"); +MODULE_LICENSE("GPL");
Implement the PWM driver for CV1800. Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-cv1800.c | 314 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 325 insertions(+) create mode 100644 drivers/pwm/pwm-cv1800.c