diff mbox series

drm/i915: Rename ICL_PORT_TX_DW6 bits

Message ID 20240308072400.28918-1-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Rename ICL_PORT_TX_DW6 bits | expand

Commit Message

Ville Syrjala March 8, 2024, 7:24 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Our definitions for bit 7 and bit 0 of ICL_PORT_TX_DW6 are
swapped. Functionally it doesn't matter as we always set both
bits, but let's rename the bits to match bspec 100%.

And while at it, add the definition for bits 1-6 as well, just
to have it all fully documented.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy_regs.h     | 5 +++--
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)

Comments

Rodrigo Vivi March 8, 2024, 3:33 p.m. UTC | #1 
On Fri, Mar 08, 2024 at 09:24:00AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Our definitions for bit 7 and bit 0 of ICL_PORT_TX_DW6 are
> swapped. Functionally it doesn't matter as we always set both
> bits, but let's rename the bits to match bspec 100%.
> 
> And while at it, add the definition for bits 1-6 as well, just
> to have it all fully documented.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_combo_phy_regs.h     | 5 +++--
>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
> index 63601129b736..0964e392d02c 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
> @@ -141,8 +141,9 @@
>  #define ICL_PORT_TX_DW6_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(6, phy))
>  #define ICL_PORT_TX_DW6_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(6, phy))
>  #define ICL_PORT_TX_DW6_LN(ln, phy)		_MMIO(_ICL_PORT_TX_DW_LN(6, ln, phy))
> -#define   ICL_AUX_ANAOVRD1_LDO_BYPASS		REG_BIT(7)
> -#define   ICL_AUX_ANAOVRD1_ENABLE		REG_BIT(0)
> +#define   O_FUNC_OVRD_EN			REG_BIT(7)
> +#define   O_LDO_REF_SEL_CRI			REG_GENMASK(6, 1)
> +#define   O_LDO_BYPASS_CRI			REG_BIT(0)

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  
>  #define ICL_PORT_TX_DW7_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
>  #define ICL_PORT_TX_DW7_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 217f82f1da84..78005d12638c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -425,7 +425,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  	if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
>  	    !intel_aux_ch_is_edp(dev_priv, ICL_AUX_PW_TO_CH(pw_idx)))
>  		intel_de_rmw(dev_priv, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)),
> -			     0, ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS);
> +			     0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI);
>  }
>  
>  static void
> -- 
> 2.43.0
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
index 63601129b736..0964e392d02c 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
@@ -141,8 +141,9 @@ 
 #define ICL_PORT_TX_DW6_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(6, phy))
 #define ICL_PORT_TX_DW6_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(6, phy))
 #define ICL_PORT_TX_DW6_LN(ln, phy)		_MMIO(_ICL_PORT_TX_DW_LN(6, ln, phy))
-#define   ICL_AUX_ANAOVRD1_LDO_BYPASS		REG_BIT(7)
-#define   ICL_AUX_ANAOVRD1_ENABLE		REG_BIT(0)
+#define   O_FUNC_OVRD_EN			REG_BIT(7)
+#define   O_LDO_REF_SEL_CRI			REG_GENMASK(6, 1)
+#define   O_LDO_BYPASS_CRI			REG_BIT(0)
 
 #define ICL_PORT_TX_DW7_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
 #define ICL_PORT_TX_DW7_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 217f82f1da84..78005d12638c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -425,7 +425,7 @@  icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 	if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
 	    !intel_aux_ch_is_edp(dev_priv, ICL_AUX_PW_TO_CH(pw_idx)))
 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)),
-			     0, ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS);
+			     0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI);
 }
 
 static void