Message ID | 2-v5-9a37e0c884ce+31e3-smmuv3_newapi_p2_jgg@nvidia.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Update SMMUv3 to the modern iommu API (part 2/3) | expand |
Reviewed-by: Michael Shavit <mshavit@google.com> On Tue, Mar 5, 2024 at 7:44 AM Jason Gunthorpe <jgg@nvidia.com> wrote: > > At this point we know which master we are going to change the PCI config > on, this is the only device we need to invalidate. Switch > arm_smmu_atc_inv_domain() for arm_smmu_atc_inv_master(). > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index d1bc151a5dff8c..9e9233331c4636 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -2447,7 +2447,10 @@ static void arm_smmu_enable_ats(struct arm_smmu_master *master, > pdev = to_pci_dev(master->dev); > > atomic_inc(&smmu_domain->nr_ats_masters); > - arm_smmu_atc_inv_domain(smmu_domain, IOMMU_NO_PASID, 0, 0); > + /* > + * ATC invalidation of PASID 0 causes the entire ATC to be flushed. > + */ > + arm_smmu_atc_inv_master(master); > if (pci_enable_ats(pdev, stu)) > dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); > } > -- > 2.43.2 > >
On Mon, Mar 04, 2024 at 07:43:50PM -0400, Jason Gunthorpe wrote: > At this point we know which master we are going to change the PCI config > on, this is the only device we need to invalidate. Switch > arm_smmu_atc_inv_domain() for arm_smmu_atc_inv_master(). > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
On Mon, Mar 04, 2024 at 07:43:50PM -0400, Jason Gunthorpe wrote: > At this point we know which master we are going to change the PCI config > on, this is the only device we need to invalidate. Switch > arm_smmu_atc_inv_domain() for arm_smmu_atc_inv_master(). > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Moritz Fischer <moritzf@google.com> > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index d1bc151a5dff8c..9e9233331c4636 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -2447,7 +2447,10 @@ static void arm_smmu_enable_ats(struct > arm_smmu_master *master, > pdev = to_pci_dev(master->dev); > atomic_inc(&smmu_domain->nr_ats_masters); > - arm_smmu_atc_inv_domain(smmu_domain, IOMMU_NO_PASID, 0, 0); > + /* > + * ATC invalidation of PASID 0 causes the entire ATC to be flushed. > + */ > + arm_smmu_atc_inv_master(master); > if (pci_enable_ats(pdev, stu)) > dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); > } > -- > 2.43.2
Hi Jason, On Mon, Mar 04, 2024 at 07:43:50PM -0400, Jason Gunthorpe wrote: > At this point we know which master we are going to change the PCI config > on, this is the only device we need to invalidate. Switch > arm_smmu_atc_inv_domain() for arm_smmu_atc_inv_master(). > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index d1bc151a5dff8c..9e9233331c4636 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -2447,7 +2447,10 @@ static void arm_smmu_enable_ats(struct arm_smmu_master *master, > pdev = to_pci_dev(master->dev); > > atomic_inc(&smmu_domain->nr_ats_masters); > - arm_smmu_atc_inv_domain(smmu_domain, IOMMU_NO_PASID, 0, 0); > + /* > + * ATC invalidation of PASID 0 causes the entire ATC to be flushed. > + */ > + arm_smmu_atc_inv_master(master); > if (pci_enable_ats(pdev, stu)) > dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); > } > -- > 2.43.2 Reviewed-by: Mostafa Saleh <smostafa@google.com> Thanks, Mostafa
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d1bc151a5dff8c..9e9233331c4636 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2447,7 +2447,10 @@ static void arm_smmu_enable_ats(struct arm_smmu_master *master, pdev = to_pci_dev(master->dev); atomic_inc(&smmu_domain->nr_ats_masters); - arm_smmu_atc_inv_domain(smmu_domain, IOMMU_NO_PASID, 0, 0); + /* + * ATC invalidation of PASID 0 causes the entire ATC to be flushed. + */ + arm_smmu_atc_inv_master(master); if (pci_enable_ats(pdev, stu)) dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); }