| Message ID | 3-v5-9a37e0c884ce+31e3-smmuv3_newapi_p2_jgg@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update SMMUv3 to the modern iommu API (part 2/3) | expand |
On Tue, Mar 5, 2024 at 7:44 AM Jason Gunthorpe <jgg@nvidia.com> wrote: > > Instead of passing a naked __le16 * around to represent a CD table entry > wrap it in a "struct arm_smmu_cd" with an array of the correct size. This > makes it much clearer which functions will comprise the "CD API". > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 20 +++++++++++--------- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 ++++++- > 2 files changed, 17 insertions(+), 10 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 9e9233331c4636..c60b067c1f553e 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1219,7 +1219,8 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst, > WRITE_ONCE(*dst, cpu_to_le64(val)); > } > > -static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) > +static struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, > + u32 ssid) > { > __le64 *l1ptr; > unsigned int idx; > @@ -1228,7 +1229,8 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) > struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; > > if (cd_table->s1fmt == STRTAB_STE_0_S1FMT_LINEAR) > - return cd_table->cdtab + ssid * CTXDESC_CD_DWORDS; > + return (struct arm_smmu_cd *)(cd_table->cdtab + > + ssid * CTXDESC_CD_DWORDS); Can we define cd_table.cdtab as a union type to avoid this cast and make the struct definition more explicit? > > idx = ssid >> CTXDESC_SPLIT; > l1_desc = &cd_table->l1_desc[idx]; > @@ -1242,7 +1244,7 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) > arm_smmu_sync_cd(master, ssid, false); > } > idx = ssid & (CTXDESC_L2_ENTRIES - 1); > - return l1_desc->l2ptr + idx * CTXDESC_CD_DWORDS; > + return &l1_desc->l2ptr[idx]; > } > > int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, > @@ -1261,7 +1263,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, > */ > u64 val; > bool cd_live; > - __le64 *cdptr; > + struct arm_smmu_cd *cdptr; > struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; > struct arm_smmu_device *smmu = master->smmu; > > @@ -1272,7 +1274,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, > if (!cdptr) > return -ENOMEM; > > - val = le64_to_cpu(cdptr[0]); > + val = le64_to_cpu(cdptr->data[0]); > cd_live = !!(val & CTXDESC_CD_0_V); > > if (!cd) { /* (5) */ > @@ -1289,9 +1291,9 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, > * this substream's traffic > */ > } else { /* (1) and (2) */ > - cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); > - cdptr[2] = 0; > - cdptr[3] = cpu_to_le64(cd->mair); > + cdptr->data[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); > + cdptr->data[2] = 0; > + cdptr->data[3] = cpu_to_le64(cd->mair); > > /* > * STE may be live, and the SMMU might read dwords of this CD in any > @@ -1323,7 +1325,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, > * field within an aligned 64-bit span of a structure can be altered > * without first making the structure invalid. > */ > - WRITE_ONCE(cdptr[0], cpu_to_le64(val)); > + WRITE_ONCE(cdptr->data[0], cpu_to_le64(val)); > arm_smmu_sync_cd(master, ssid, true); > return 0; > } > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 23baf117e7e4b5..7078ed569fd4d3 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -282,6 +282,11 @@ struct arm_smmu_ste { > #define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12) > > #define CTXDESC_CD_DWORDS 8 > + > +struct arm_smmu_cd { > + __le64 data[CTXDESC_CD_DWORDS]; > +}; > + > #define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) > #define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6) > #define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8) > @@ -591,7 +596,7 @@ struct arm_smmu_ctx_desc { > }; > > struct arm_smmu_l1_ctx_desc { > - __le64 *l2ptr; > + struct arm_smmu_cd *l2ptr; > dma_addr_t l2ptr_dma; > }; > > -- > 2.43.2 > > Reviewed-by: Michael Shavit <mshavit@google.com>
On Mon, Mar 04, 2024 at 07:43:51PM -0400, Jason Gunthorpe wrote: > Instead of passing a naked __le16 * around to represent a CD table entry > wrap it in a "struct arm_smmu_cd" with an array of the correct size. This > makes it much clearer which functions will comprise the "CD API". > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
On Wed, Mar 13, 2024 at 05:44:35PM +0800, Michael Shavit wrote: > On Tue, Mar 5, 2024 at 7:44 AM Jason Gunthorpe <jgg@nvidia.com> wrote: > > > > Instead of passing a naked __le16 * around to represent a CD table entry > > wrap it in a "struct arm_smmu_cd" with an array of the correct size. > This > > makes it much clearer which functions will comprise the "CD API". > > > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 20 +++++++++++--------- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 ++++++- > > 2 files changed, 17 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index 9e9233331c4636..c60b067c1f553e 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -1219,7 +1219,8 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst, > > WRITE_ONCE(*dst, cpu_to_le64(val)); > > } > > > > -static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 > ssid) > > +static struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master > *master, > > + u32 ssid) > > { > > __le64 *l1ptr; > > unsigned int idx; > > @@ -1228,7 +1229,8 @@ static __le64 *arm_smmu_get_cd_ptr(struct > arm_smmu_master *master, u32 ssid) > > struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; > > > > if (cd_table->s1fmt == STRTAB_STE_0_S1FMT_LINEAR) > > - return cd_table->cdtab + ssid * CTXDESC_CD_DWORDS; > > + return (struct arm_smmu_cd *)(cd_table->cdtab + > > + ssid * CTXDESC_CD_DWORDS); > Can we define cd_table.cdtab as a union type to avoid this cast and > make the struct definition more explicit? +1, I think that'd make it more readable. > > > > idx = ssid >> CTXDESC_SPLIT; > > l1_desc = &cd_table->l1_desc[idx]; > > @@ -1242,7 +1244,7 @@ static __le64 *arm_smmu_get_cd_ptr(struct > arm_smmu_master *master, u32 ssid) > > arm_smmu_sync_cd(master, ssid, false); > > } > > idx = ssid & (CTXDESC_L2_ENTRIES - 1); > > - return l1_desc->l2ptr + idx * CTXDESC_CD_DWORDS; > > + return &l1_desc->l2ptr[idx]; > > } > > > > int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, > > @@ -1261,7 +1263,7 @@ int arm_smmu_write_ctx_desc(struct > arm_smmu_master *master, int ssid, > > */ > > u64 val; > > bool cd_live; > > - __le64 *cdptr; > > + struct arm_smmu_cd *cdptr; > > struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; > > struct arm_smmu_device *smmu = master->smmu; > > > > @@ -1272,7 +1274,7 @@ int arm_smmu_write_ctx_desc(struct > arm_smmu_master *master, int ssid, > > if (!cdptr) > > return -ENOMEM; > > > > - val = le64_to_cpu(cdptr[0]); > > + val = le64_to_cpu(cdptr->data[0]); > > cd_live = !!(val & CTXDESC_CD_0_V); > > > > if (!cd) { /* (5) */ > > @@ -1289,9 +1291,9 @@ int arm_smmu_write_ctx_desc(struct > arm_smmu_master *master, int ssid, > > * this substream's traffic > > */ > > } else { /* (1) and (2) */ > > - cdptr[1] = cpu_to_le64(cd->ttbr & > CTXDESC_CD_1_TTB0_MASK); > > - cdptr[2] = 0; > > - cdptr[3] = cpu_to_le64(cd->mair); > > + cdptr->data[1] = cpu_to_le64(cd->ttbr & > CTXDESC_CD_1_TTB0_MASK); > > + cdptr->data[2] = 0; > > + cdptr->data[3] = cpu_to_le64(cd->mair); > > > > /* > > * STE may be live, and the SMMU might read dwords of > this CD in any > > @@ -1323,7 +1325,7 @@ int arm_smmu_write_ctx_desc(struct > arm_smmu_master *master, int ssid, > > * field within an aligned 64-bit span of a structure can be > altered > > * without first making the structure invalid. > > */ > > - WRITE_ONCE(cdptr[0], cpu_to_le64(val)); > > + WRITE_ONCE(cdptr->data[0], cpu_to_le64(val)); > > arm_smmu_sync_cd(master, ssid, true); > > return 0; > > } > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > index 23baf117e7e4b5..7078ed569fd4d3 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > @@ -282,6 +282,11 @@ struct arm_smmu_ste { > > #define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12) > > > > #define CTXDESC_CD_DWORDS 8 > > + > > +struct arm_smmu_cd { > > + __le64 data[CTXDESC_CD_DWORDS]; > > +}; > > + > > #define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) > > #define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6) > > #define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8) > > @@ -591,7 +596,7 @@ struct arm_smmu_ctx_desc { > > }; > > > > struct arm_smmu_l1_ctx_desc { > > - __le64 *l2ptr; > > + struct arm_smmu_cd *l2ptr; > > dma_addr_t l2ptr_dma; > > }; > > > > -- > > 2.43.2 > > > > > Reviewed-by: Michael Shavit <mshavit@google.com> Reviewed-by: Moritz Fischer <moritzf@google.com>
On Wed, Mar 13, 2024 at 05:44:35PM +0800, Michael Shavit wrote: > On Tue, Mar 5, 2024 at 7:44 AM Jason Gunthorpe <jgg@nvidia.com> wrote: > > > > Instead of passing a naked __le16 * around to represent a CD table entry > > wrap it in a "struct arm_smmu_cd" with an array of the correct size. This > > makes it much clearer which functions will comprise the "CD API". > > > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 20 +++++++++++--------- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 ++++++- > > 2 files changed, 17 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index 9e9233331c4636..c60b067c1f553e 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -1219,7 +1219,8 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst, > > WRITE_ONCE(*dst, cpu_to_le64(val)); > > } > > > > -static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) > > +static struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, > > + u32 ssid) > > { > > __le64 *l1ptr; > > unsigned int idx; > > @@ -1228,7 +1229,8 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) > > struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; > > > > if (cd_table->s1fmt == STRTAB_STE_0_S1FMT_LINEAR) > > - return cd_table->cdtab + ssid * CTXDESC_CD_DWORDS; > > + return (struct arm_smmu_cd *)(cd_table->cdtab + > > + ssid * CTXDESC_CD_DWORDS); > > Can we define cd_table.cdtab as a union type to avoid this cast and > make the struct definition more explicit? Yes, those patches are in part 3 to fix the CD and STE to be like you suggest. In the end the above looks like: if (cd_table->s1fmt == STRTAB_STE_0_S1FMT_LINEAR) return cd_table->cdtab.linear + ssid; Thanks, Jason
On Mon, Mar 04, 2024 at 07:43:51PM -0400, Jason Gunthorpe wrote: > Instead of passing a naked __le16 * around to represent a CD table entry > wrap it in a "struct arm_smmu_cd" with an array of the correct size. This > makes it much clearer which functions will comprise the "CD API". > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 20 +++++++++++--------- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 ++++++- > 2 files changed, 17 insertions(+), 10 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 9e9233331c4636..c60b067c1f553e 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1219,7 +1219,8 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst, > WRITE_ONCE(*dst, cpu_to_le64(val)); > } > > -static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) > +static struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, > + u32 ssid) > { > __le64 *l1ptr; > unsigned int idx; > @@ -1228,7 +1229,8 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) > struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; > > if (cd_table->s1fmt == STRTAB_STE_0_S1FMT_LINEAR) > - return cd_table->cdtab + ssid * CTXDESC_CD_DWORDS; > + return (struct arm_smmu_cd *)(cd_table->cdtab + > + ssid * CTXDESC_CD_DWORDS); > > idx = ssid >> CTXDESC_SPLIT; > l1_desc = &cd_table->l1_desc[idx]; > @@ -1242,7 +1244,7 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) > arm_smmu_sync_cd(master, ssid, false); > } > idx = ssid & (CTXDESC_L2_ENTRIES - 1); > - return l1_desc->l2ptr + idx * CTXDESC_CD_DWORDS; > + return &l1_desc->l2ptr[idx]; > } > > int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, > @@ -1261,7 +1263,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, > */ > u64 val; > bool cd_live; > - __le64 *cdptr; > + struct arm_smmu_cd *cdptr; > struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; > struct arm_smmu_device *smmu = master->smmu; > > @@ -1272,7 +1274,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, > if (!cdptr) > return -ENOMEM; > > - val = le64_to_cpu(cdptr[0]); > + val = le64_to_cpu(cdptr->data[0]); > cd_live = !!(val & CTXDESC_CD_0_V); > > if (!cd) { /* (5) */ > @@ -1289,9 +1291,9 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, > * this substream's traffic > */ > } else { /* (1) and (2) */ > - cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); > - cdptr[2] = 0; > - cdptr[3] = cpu_to_le64(cd->mair); > + cdptr->data[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); > + cdptr->data[2] = 0; > + cdptr->data[3] = cpu_to_le64(cd->mair); > > /* > * STE may be live, and the SMMU might read dwords of this CD in any > @@ -1323,7 +1325,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, > * field within an aligned 64-bit span of a structure can be altered > * without first making the structure invalid. > */ > - WRITE_ONCE(cdptr[0], cpu_to_le64(val)); > + WRITE_ONCE(cdptr->data[0], cpu_to_le64(val)); > arm_smmu_sync_cd(master, ssid, true); > return 0; > } > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 23baf117e7e4b5..7078ed569fd4d3 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -282,6 +282,11 @@ struct arm_smmu_ste { > #define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12) > > #define CTXDESC_CD_DWORDS 8 > + > +struct arm_smmu_cd { > + __le64 data[CTXDESC_CD_DWORDS]; > +}; > + > #define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) > #define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6) > #define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8) > @@ -591,7 +596,7 @@ struct arm_smmu_ctx_desc { > }; > > struct arm_smmu_l1_ctx_desc { > - __le64 *l2ptr; > + struct arm_smmu_cd *l2ptr; > dma_addr_t l2ptr_dma; > }; > > -- > 2.43.2 > Reviewed-by: Mostafa Saleh <smostafa@google.com> Thanks, Mostafa
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 9e9233331c4636..c60b067c1f553e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1219,7 +1219,8 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst, WRITE_ONCE(*dst, cpu_to_le64(val)); } -static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) +static struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, + u32 ssid) { __le64 *l1ptr; unsigned int idx; @@ -1228,7 +1229,8 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; if (cd_table->s1fmt == STRTAB_STE_0_S1FMT_LINEAR) - return cd_table->cdtab + ssid * CTXDESC_CD_DWORDS; + return (struct arm_smmu_cd *)(cd_table->cdtab + + ssid * CTXDESC_CD_DWORDS); idx = ssid >> CTXDESC_SPLIT; l1_desc = &cd_table->l1_desc[idx]; @@ -1242,7 +1244,7 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) arm_smmu_sync_cd(master, ssid, false); } idx = ssid & (CTXDESC_L2_ENTRIES - 1); - return l1_desc->l2ptr + idx * CTXDESC_CD_DWORDS; + return &l1_desc->l2ptr[idx]; } int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, @@ -1261,7 +1263,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, */ u64 val; bool cd_live; - __le64 *cdptr; + struct arm_smmu_cd *cdptr; struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; struct arm_smmu_device *smmu = master->smmu; @@ -1272,7 +1274,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, if (!cdptr) return -ENOMEM; - val = le64_to_cpu(cdptr[0]); + val = le64_to_cpu(cdptr->data[0]); cd_live = !!(val & CTXDESC_CD_0_V); if (!cd) { /* (5) */ @@ -1289,9 +1291,9 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, * this substream's traffic */ } else { /* (1) and (2) */ - cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); - cdptr[2] = 0; - cdptr[3] = cpu_to_le64(cd->mair); + cdptr->data[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); + cdptr->data[2] = 0; + cdptr->data[3] = cpu_to_le64(cd->mair); /* * STE may be live, and the SMMU might read dwords of this CD in any @@ -1323,7 +1325,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, * field within an aligned 64-bit span of a structure can be altered * without first making the structure invalid. */ - WRITE_ONCE(cdptr[0], cpu_to_le64(val)); + WRITE_ONCE(cdptr->data[0], cpu_to_le64(val)); arm_smmu_sync_cd(master, ssid, true); return 0; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 23baf117e7e4b5..7078ed569fd4d3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -282,6 +282,11 @@ struct arm_smmu_ste { #define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12) #define CTXDESC_CD_DWORDS 8 + +struct arm_smmu_cd { + __le64 data[CTXDESC_CD_DWORDS]; +}; + #define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) #define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6) #define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8) @@ -591,7 +596,7 @@ struct arm_smmu_ctx_desc { }; struct arm_smmu_l1_ctx_desc { - __le64 *l2ptr; + struct arm_smmu_cd *l2ptr; dma_addr_t l2ptr_dma; };