| Message ID | 20240318-pci-bdf-sid-fix-v1-2-acca6c5d9cf1@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 398b7c7dda6792c2646a2208a6cbab02da97d6e5 |
| Headers | show |
| Series | arm64: dts: qcom: Fix the msi-map entries | expand |
On 18/03/2024 08:19, Manivannan Sadhasivam wrote: > While adding the GIC ITS MSI support, it was found that the msi-map entries > needed to be swapped to receive MSIs from the endpoint. > > But later it was identified that the swapping was needed due to a bug in > the Qualcomm PCIe controller driver. And since the bug is now fixed with > commit bf79e33cdd89 ("PCI: qcom: Enable BDF to SID translation properly"), > let's fix the msi-map entries also to reflect the actual mapping in the > hardware. > > Fixes: 114990ce3edf ("arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1") > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++++------ > 1 file changed, 4 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 3904348075f6..3348bc06db48 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1755,9 +1755,8 @@ pcie0: pcie@1c00000 { > <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; > interconnect-names = "pcie-mem", "cpu-pcie"; > > - /* Entries are reversed due to the unusual ITS DeviceID encoding */ > - msi-map = <0x0 &gic_its 0x1401 0x1>, > - <0x100 &gic_its 0x1400 0x1>; > + msi-map = <0x0 &gic_its 0x1400 0x1>, > + <0x100 &gic_its 0x1401 0x1>; > iommu-map = <0x0 &apps_smmu 0x1400 0x1>, > <0x100 &apps_smmu 0x1401 0x1>; > > @@ -1867,9 +1866,8 @@ pcie1: pcie@1c08000 { > <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; > interconnect-names = "pcie-mem", "cpu-pcie"; > > - /* Entries are reversed due to the unusual ITS DeviceID encoding */ > - msi-map = <0x0 &gic_its 0x1481 0x1>, > - <0x100 &gic_its 0x1480 0x1>; > + msi-map = <0x0 &gic_its 0x1480 0x1>, > + <0x100 &gic_its 0x1481 0x1>; > iommu-map = <0x0 &apps_smmu 0x1480 0x1>, > <0x100 &apps_smmu 0x1481 0x1>; > > Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 3904348075f6..3348bc06db48 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1755,9 +1755,8 @@ pcie0: pcie@1c00000 { <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - /* Entries are reversed due to the unusual ITS DeviceID encoding */ - msi-map = <0x0 &gic_its 0x1401 0x1>, - <0x100 &gic_its 0x1400 0x1>; + msi-map = <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; iommu-map = <0x0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; @@ -1867,9 +1866,8 @@ pcie1: pcie@1c08000 { <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - /* Entries are reversed due to the unusual ITS DeviceID encoding */ - msi-map = <0x0 &gic_its 0x1481 0x1>, - <0x100 &gic_its 0x1480 0x1>; + msi-map = <0x0 &gic_its 0x1480 0x1>, + <0x100 &gic_its 0x1481 0x1>; iommu-map = <0x0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>;
While adding the GIC ITS MSI support, it was found that the msi-map entries needed to be swapped to receive MSIs from the endpoint. But later it was identified that the swapping was needed due to a bug in the Qualcomm PCIe controller driver. And since the bug is now fixed with commit bf79e33cdd89 ("PCI: qcom: Enable BDF to SID translation properly"), let's fix the msi-map entries also to reflect the actual mapping in the hardware. Fixes: 114990ce3edf ("arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)