diff mbox series

[13/14] mips: dts: ralink: mt7621: reorder pci?_phy attributes

Message ID 20240316045442.31469-14-justin.swartz@risingedge.co.za (mailing list archive)
State Accepted
Commit de56f781e5483fb3b3527aa280df2434f0cb2ace
Headers show
Series mips: dts: ralink: mt7621: improve DTS style | expand

Commit Message

Justin Swartz March 16, 2024, 4:54 a.m. UTC 
Reorder the attributes of the PCIe PHY nodes node to match
what the DTS style guide recommends.

Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
---
 arch/mips/boot/dts/ralink/mt7621.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

--

Comments

Arınç ÜNAL March 16, 2024, 9:23 a.m. UTC | #1 
On 16.03.2024 07:54, Justin Swartz wrote:
> Reorder the attributes of the PCIe PHY nodes node to match
> what the DTS style guide recommends.
> 
> Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>

Reviewed-by: Arınç ÜNAL <arinc.unal@arinc9.com>

Arınç
AngeloGioacchino Del Regno March 18, 2024, 10:20 a.m. UTC | #2 
Il 16/03/24 05:54, Justin Swartz ha scritto:
> Reorder the attributes of the PCIe PHY nodes node to match
> what the DTS style guide recommends.
> 
> Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
diff mbox series

Patch

diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index aa06d12ac..284811f32 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -583,14 +583,18 @@  pcie@2,0 {
 	pcie0_phy: pcie-phy@1e149000 {
 		compatible = "mediatek,mt7621-pci-phy";
 		reg = <0x1e149000 0x0700>;
-		clocks = <&sysc MT7621_CLK_XTAL>;
+
 		#phy-cells = <1>;
+
+		clocks = <&sysc MT7621_CLK_XTAL>;
 	};
 
 	pcie2_phy: pcie-phy@1e14a000 {
 		compatible = "mediatek,mt7621-pci-phy";
 		reg = <0x1e14a000 0x0700>;
-		clocks = <&sysc MT7621_CLK_XTAL>;
+
 		#phy-cells = <1>;
+
+		clocks = <&sysc MT7621_CLK_XTAL>;
 	};
 };