| Message ID | 20240314-imx95-blk-ctl-v4-5-d23de23b6ff2@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support i.MX95 BLK CTL module clock features | expand |
On 14/03/2024 14:25, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > The DISPLAY_CSR provides control and status of the following: > Clock selection for the Display Engines > Pixel Interleaver mode selection > Pixel Link enables > QoS settings for the display controller > ArCache and AwCache signals > Display Engine plane association > > This patch is to add the clock features for this module > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > .../bindings/clock/nxp,imx95-display-csr.yaml | 50 ++++++++++++++++++++++ > include/dt-bindings/clock/nxp,imx95-clock.h | 4 ++ > 2 files changed, 54 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml > new file mode 100644 > index 000000000000..9a5e21346b0d > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml > @@ -0,0 +1,50 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/nxp,imx95-display-csr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX95 Display Block Control > + > +maintainers: > + - Peng Fan <peng.fan@nxp.com> > + > +properties: > + compatible: > + items: > + - const: nxp,imx95-display-csr > + - const: syscon Why do you create five different bindings with almost the same contents? Do you plan to grow on them, like add more compatibles here? Otherwise all this could be in one binding. Best regards, Krzysztof
> Subject: Re: [PATCH v4 5/6] dt-bindindgs: clock: nxp: support i.MX95 Display > CSR module > > On 14/03/2024 14:25, Peng Fan (OSS) wrote: > > From: Peng Fan <peng.fan@nxp.com> > > > > The DISPLAY_CSR provides control and status of the following: > > Clock selection for the Display Engines Pixel Interleaver mode > > selection Pixel Link enables QoS settings for the display controller > > ArCache and AwCache signals Display Engine plane association > > > > This patch is to add the clock features for this module > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > .../bindings/clock/nxp,imx95-display-csr.yaml | 50 > ++++++++++++++++++++++ > > include/dt-bindings/clock/nxp,imx95-clock.h | 4 ++ > > 2 files changed, 54 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml > > b/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml > > new file mode 100644 > > index 000000000000..9a5e21346b0d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.ya > > +++ ml > > @@ -0,0 +1,50 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > +cetree.org%2Fschemas%2Fclock%2Fnxp%2Cimx95-display- > csr.yaml%23&data=0 > > > +5%7C02%7Cpeng.fan%40nxp.com%7C479f8c47bd4d421a669708dc45316f1 > 2%7C686e > > > +a1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638461325839625184%7 > CUnknown%7 > > > +CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW > wiLCJX > > > +VCI6Mn0%3D%7C0%7C%7C%7C&sdata=rntSlDs8ASXSb3L%2F9ZCzgW%2Bzo > v2LU9vcTD7 > > +SvjE37Nw%3D&reserved=0 > > +$schema: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > +cetree.org%2Fmeta- > schemas%2Fcore.yaml%23&data=05%7C02%7Cpeng.fan%40nx > > > +p.com%7C479f8c47bd4d421a669708dc45316f12%7C686ea1d3bc2b4c6fa9 > 2cd99c5c > > > +301635%7C0%7C0%7C638461325839637072%7CUnknown%7CTWFpbGZs > b3d8eyJWIjoiM > > > +C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7 > C%7C%7 > > > +C&sdata=%2BjYpR8p7IDjRzV39hJhtv8FozALx9HqqLhoFgwBJCm4%3D&reserv > ed=0 > > + > > +title: NXP i.MX95 Display Block Control > > + > > +maintainers: > > + - Peng Fan <peng.fan@nxp.com> > > + > > +properties: > > + compatible: > > + items: > > + - const: nxp,imx95-display-csr > > + - const: syscon > > Why do you create five different bindings with almost the same contents? > Do you plan to grow on them, like add more compatibles here? Otherwise all > this could be in one binding. The blk ctrls are for different functions. We may expand the bindings to add more properties for the blk ctrls, but I am not sure as of now. I could merge them into one binding except the one with mux-controller if you prefer. Or leave them as is, still separate binding files. Thanks, Peng. > > Best regards, > Krzysztof
On 18/03/2024 13:37, Peng Fan wrote: >>> + >>> +maintainers: >>> + - Peng Fan <peng.fan@nxp.com> >>> + >>> +properties: >>> + compatible: >>> + items: >>> + - const: nxp,imx95-display-csr >>> + - const: syscon >> >> Why do you create five different bindings with almost the same contents? >> Do you plan to grow on them, like add more compatibles here? Otherwise all >> this could be in one binding. > > The blk ctrls are for different functions. > > We may expand the bindings to add more properties for the blk ctrls, but I > am not sure as of now. I could merge them into one binding except Bindings should be complete... Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml new file mode 100644 index 000000000000..9a5e21346b0d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nxp,imx95-display-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX95 Display Block Control + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +properties: + compatible: + items: + - const: nxp,imx95-display-csr + - const: syscon + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See + include/dt-bindings/clock/nxp,imx95-clock.h + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + syscon@4c410000 { + compatible = "nxp,imx95-display-csr", "syscon"; + reg = <0x4b010000 0x10000>; + #clock-cells = <1>; + clocks = <&scmi_clk 75>; + power-domains = <&scmi_devpd 13>; + }; +... diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h index e642a54c81a0..83fa3ffe78a8 100644 --- a/include/dt-bindings/clock/nxp,imx95-clock.h +++ b/include/dt-bindings/clock/nxp,imx95-clock.h @@ -25,4 +25,8 @@ #define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4 #define IMX95_CLK_DISPMIX_LVDS_CSR_END 5 +#define IMX95_CLK_DISPMIX_ENG0_SEL 0 +#define IMX95_CLK_DISPMIX_ENG1_SEL 1 +#define IMX95_CLK_DISPMIX_END 2 + #endif /* __DT_BINDINGS_CLOCK_IMX95_H */