| Message ID | IA1PR20MB4953EE73DD36D5FFC81D90EDBB352@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | riscv: sophgo: add support for usb controller of CV18XX/SG200X | expand |
On 3/26/24 06:37, Inochi Amaoto wrote: > Add params for DWC2 IP in Sophgo CV18XX/SG200X series SoC. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Acked-by: Minas Harutyunyan <hminas@synopsys.com> > --- > drivers/usb/dwc2/params.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c > index eb677c3cfd0b..171fcb34eb75 100644 > --- a/drivers/usb/dwc2/params.c > +++ b/drivers/usb/dwc2/params.c > @@ -201,6 +201,25 @@ static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) > p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; > } > > +static void dwc2_set_cv1800_params(struct dwc2_hsotg *hsotg) > +{ > + struct dwc2_core_params *p = &hsotg->params; > + > + p->otg_caps.hnp_support = false; > + p->otg_caps.srp_support = false; > + p->host_dma = false; > + p->g_dma = false; > + p->speed = DWC2_SPEED_PARAM_HIGH; > + p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; > + p->phy_utmi_width = 16; > + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; > + p->lpm = false; > + p->lpm_clock_gating = false; > + p->besl = false; > + p->hird_threshold_en = false; > + p->power_down = DWC2_POWER_DOWN_PARAM_NONE; > +} > + > static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) > { > struct dwc2_core_params *p = &hsotg->params; > @@ -295,6 +314,8 @@ const struct of_device_id dwc2_of_match_table[] = { > .data = dwc2_set_amlogic_a1_params }, > { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, > { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, > + { .compatible = "sophgo,cv1800-usb", > + .data = dwc2_set_cv1800_params }, > { .compatible = "st,stm32f4x9-fsotg", > .data = dwc2_set_stm32f4x9_fsotg_params }, > { .compatible = "st,stm32f4x9-hsotg" }, > -- > 2.44.0 >
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c index eb677c3cfd0b..171fcb34eb75 100644 --- a/drivers/usb/dwc2/params.c +++ b/drivers/usb/dwc2/params.c @@ -201,6 +201,25 @@ static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; } +static void dwc2_set_cv1800_params(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *p = &hsotg->params; + + p->otg_caps.hnp_support = false; + p->otg_caps.srp_support = false; + p->host_dma = false; + p->g_dma = false; + p->speed = DWC2_SPEED_PARAM_HIGH; + p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; + p->phy_utmi_width = 16; + p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; + p->lpm = false; + p->lpm_clock_gating = false; + p->besl = false; + p->hird_threshold_en = false; + p->power_down = DWC2_POWER_DOWN_PARAM_NONE; +} + static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) { struct dwc2_core_params *p = &hsotg->params; @@ -295,6 +314,8 @@ const struct of_device_id dwc2_of_match_table[] = { .data = dwc2_set_amlogic_a1_params }, { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, + { .compatible = "sophgo,cv1800-usb", + .data = dwc2_set_cv1800_params }, { .compatible = "st,stm32f4x9-fsotg", .data = dwc2_set_stm32f4x9_fsotg_params }, { .compatible = "st,stm32f4x9-hsotg" },
Add params for DWC2 IP in Sophgo CV18XX/SG200X series SoC. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- drivers/usb/dwc2/params.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.44.0