diff mbox series

clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018

Message ID 20240326-fix-ipq5018-apss-pll-rate-v1-1-82ab31c9da7e@gmail.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018 | expand

Commit Message

Gabor Juhos March 26, 2024, 1:34 p.m. UTC
According to ipq5018.dtsi, the maximum supported rate by the
CPU is 1.008 GHz on the IPQ5018 platform, however the current
configuration of the PLL results in 1.2 GHz rate.

Change the 'L' value in the PLL configuration to limit the
rate to 1.008 GHz. The downstream kernel also uses the same
value [1]. Also add a comment to indicate the desired
frequency.

[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c?ref_type=heads#L151

Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
Based on v6.9-rc1.

Note: The change is independent from the "clk: qcom: apss-ipq-pll: various
cleanups" series posted earlier [2].

[2] https://lore.kernel.org/r/20240326-apss-ipq-pll-cleanup-v3-0-15c4aeeb14ac@gmail.com
---
 drivers/clk/qcom/apss-ipq-pll.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)


---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240326-fix-ipq5018-apss-pll-rate-fed3ab51b1c2

Best regards,

Comments

Konrad Dybcio March 26, 2024, 8:48 p.m. UTC | #1
On 26.03.2024 2:34 PM, Gabor Juhos wrote:
> According to ipq5018.dtsi, the maximum supported rate by the
> CPU is 1.008 GHz on the IPQ5018 platform, however the current
> configuration of the PLL results in 1.2 GHz rate.
> 
> Change the 'L' value in the PLL configuration to limit the
> rate to 1.008 GHz. The downstream kernel also uses the same
> value [1]. Also add a comment to indicate the desired
> frequency.
> 
> [1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c?ref_type=heads#L151
> 
> Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018")
> Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
Bjorn Andersson April 27, 2024, 7:34 p.m. UTC | #2
On Tue, 26 Mar 2024 14:34:11 +0100, Gabor Juhos wrote:
> According to ipq5018.dtsi, the maximum supported rate by the
> CPU is 1.008 GHz on the IPQ5018 platform, however the current
> configuration of the PLL results in 1.2 GHz rate.
> 
> Change the 'L' value in the PLL configuration to limit the
> rate to 1.008 GHz. The downstream kernel also uses the same
> value [1]. Also add a comment to indicate the desired
> frequency.
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
      commit: f58edff0331fa18bbaaade3ae675f547c0245224

Best regards,
diff mbox series

Patch

diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
index 678b805f13d45..5e3da5558f4e0 100644
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -73,8 +73,9 @@  static struct clk_alpha_pll ipq_pll_stromer_plus = {
 	},
 };
 
+/* 1.008 GHz configuration */
 static const struct alpha_pll_config ipq5018_pll_config = {
-	.l = 0x32,
+	.l = 0x2a,
 	.config_ctl_val = 0x4001075b,
 	.config_ctl_hi_val = 0x304,
 	.main_output_mask = BIT(0),