| Message ID | 20240327174544.983-1-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | drm/i915: Implemnt vblank sycnhronized mbus joining changes | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville > Syrjala > Sent: Wednesday, March 27, 2024 11:16 PM > To: intel-gfx@lists.freedesktop.org > Subject: [PATCH 00/13] drm/i915: Implemnt vblank sycnhronized mbus joining > changes Nit: Typo in implement and synchronized > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Get rid of the full modeset requirement for changing mbus joining. Things got > quite a bit more complicated than originally envisioned due to the dynamic > cdclk/mdclk ratio. > Sadly we have to do a fairly careful dance between the dbuf and cdclk code to > make sure everything is programmed in the correct sequence. > > Stan did the grunt work, but the sequence vs. cdclk updates was still not right so I > finished that part. > I also reorganized the code quite a bit to make the resulting patches more legible. > And I tossed in more debugs and whatnot so we can actually observe what it's > doing. > > Quickly smoke tested on tgl and adl, and things seem pretty decent. > Unfortunately I don't have a LNL on me right now so I haven't fully tested the > mdclk/cdclk ratio changes on real hw, but I did hack my adl to pretend that the > ratio changes with cdclk and double checked that the logs look sensible for all the > combinations of cdclk increase/decrease and mbus join enable/disable. > So should work (tm) on real hw too. Reviewed the series and it looks good to me. This is ready for merge. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Regards, Uma Shankar > Stanislav Lisovskiy (3): > drm/i915: Loop over all active pipes in intel_mbus_dbox_update > drm/i915: Use old mbus_join value when increasing CDCLK > drm/i915: Implement vblank synchronized MBUS join changes > > Ville Syrjälä (10): > drm/i915/cdclk: Fix CDCLK programming order when pipes are active > drm/i915/cdclk: Fix voltage_level programming edge case > drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacks > drm/i915/cdclk: Indicate whether CDCLK change happens during pre or > post plane update > drm/i915: Relocate intel_mbus_dbox_update() > drm/i915: Extract intel_dbuf_mbus_join_update() > drm/i915: Extract intel_dbuf_mdclk_min_tracker_update() > drm/i915: Add debugs for mbus joining and dbuf ratio programming > drm/i915: Use a plain old int for the cdclk/mdclk ratio > drm/i915: Optimize out redundant dbuf slice updates > > drivers/gpu/drm/i915/display/intel_cdclk.c | 85 +++-- > drivers/gpu/drm/i915/display/intel_cdclk.h | 8 +- > drivers/gpu/drm/i915/display/intel_display.c | 5 +- > drivers/gpu/drm/i915/display/skl_watermark.c | 344 ++++++++++++------- > drivers/gpu/drm/i915/display/skl_watermark.h | 9 +- > 5 files changed, 271 insertions(+), 180 deletions(-) > > -- > 2.43.2
From: Ville Syrjälä <ville.syrjala@linux.intel.com> Get rid of the full modeset requirement for changing mbus joining. Things got quite a bit more complicated than originally envisioned due to the dynamic cdclk/mdclk ratio. Sadly we have to do a fairly careful dance between the dbuf and cdclk code to make sure everything is programmed in the correct sequence. Stan did the grunt work, but the sequence vs. cdclk updates was still not right so I finished that part. I also reorganized the code quite a bit to make the resulting patches more legible. And I tossed in more debugs and whatnot so we can actually observe what it's doing. Quickly smoke tested on tgl and adl, and things seem pretty decent. Unfortunately I don't have a LNL on me right now so I haven't fully tested the mdclk/cdclk ratio changes on real hw, but I did hack my adl to pretend that the ratio changes with cdclk and double checked that the logs look sensible for all the combinations of cdclk increase/decrease and mbus join enable/disable. So should work (tm) on real hw too. Stanislav Lisovskiy (3): drm/i915: Loop over all active pipes in intel_mbus_dbox_update drm/i915: Use old mbus_join value when increasing CDCLK drm/i915: Implement vblank synchronized MBUS join changes Ville Syrjälä (10): drm/i915/cdclk: Fix CDCLK programming order when pipes are active drm/i915/cdclk: Fix voltage_level programming edge case drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacks drm/i915/cdclk: Indicate whether CDCLK change happens during pre or post plane update drm/i915: Relocate intel_mbus_dbox_update() drm/i915: Extract intel_dbuf_mbus_join_update() drm/i915: Extract intel_dbuf_mdclk_min_tracker_update() drm/i915: Add debugs for mbus joining and dbuf ratio programming drm/i915: Use a plain old int for the cdclk/mdclk ratio drm/i915: Optimize out redundant dbuf slice updates drivers/gpu/drm/i915/display/intel_cdclk.c | 85 +++-- drivers/gpu/drm/i915/display/intel_cdclk.h | 8 +- drivers/gpu/drm/i915/display/intel_display.c | 5 +- drivers/gpu/drm/i915/display/skl_watermark.c | 344 ++++++++++++------- drivers/gpu/drm/i915/display/skl_watermark.h | 9 +- 5 files changed, 271 insertions(+), 180 deletions(-)