| Message ID | 20240329-m4_lpuart-v4-1-c11d9ca2a317@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: imx8: add cm40 and cm40_uart | expand |
On Fri, Mar 29, 2024 at 12:37:05PM -0400, Frank Li wrote: >From: Dong Aisheng <aisheng.dong@nxp.com> > >Add cm40 subsystem dtsi. > >Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> >Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> >Signed-off-by: Frank Li <Frank.Li@nxp.com> >--- > arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 67 +++++++++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 + > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 + > 3 files changed, 70 insertions(+) > >diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi >new file mode 100644 >index 0000000000000..10a05db06ade9 >--- /dev/null >+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi >@@ -0,0 +1,67 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+/* >+ * Copyright 2019 NXP The time needs to be 2024, otherwise LGTM: Reviewed-by: Peng Fan <peng.fan@nxp.com> >+ * Dong Aisheng <aisheng.dong@nxp.com> >+ */ >+ >+#include <dt-bindings/firmware/imx/rsrc.h> >+ >+cm40_ipg_clk: clock-cm40-ipg { >+ compatible = "fixed-clock"; >+ #clock-cells = <0>; >+ clock-frequency = <132000000>; >+ clock-output-names = "cm40_ipg_clk"; >+}; >+ >+cm40_subsys: bus@34000000 { >+ compatible = "simple-bus"; >+ #address-cells = <1>; >+ #size-cells = <1>; >+ ranges = <0x34000000 0x0 0x34000000 0x4000000>; >+ interrupt-parent = <&cm40_intmux>; >+ >+ cm40_i2c: i2c@37230000 { >+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; >+ reg = <0x37230000 0x1000>; >+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; >+ clocks = <&cm40_i2c_lpcg IMX_LPCG_CLK_0>, >+ <&cm40_i2c_lpcg IMX_LPCG_CLK_4>; >+ clock-names = "per", "ipg"; >+ assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>; >+ assigned-clock-rates = <24000000>; >+ power-domains = <&pd IMX_SC_R_M4_0_I2C>; >+ status = "disabled"; >+ }; >+ >+ cm40_intmux: intmux@37400000 { >+ compatible = "fsl,imx-intmux"; >+ reg = <0x37400000 0x1000>; >+ interrupt-parent = <&gic>; >+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, >+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, >+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, >+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, >+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, >+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, >+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, >+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; >+ interrupt-controller; >+ #interrupt-cells = <2>; >+ clocks = <&cm40_ipg_clk>; >+ clock-names = "ipg"; >+ power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; >+ status = "disabled"; >+ }; >+ >+ cm40_i2c_lpcg: clock-controller@37630000 { >+ compatible = "fsl,imx8qxp-lpcg"; >+ reg = <0x37630000 0x1000>; >+ #clock-cells = <1>; >+ clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>, >+ <&cm40_ipg_clk>; >+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; >+ clock-output-names = "cm40_lpcg_i2c_clk", >+ "cm40_lpcg_i2c_ipg_clk"; >+ power-domains = <&pd IMX_SC_R_M4_0_I2C>; >+ }; >+}; >diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi >index a0674c5c55766..9d49c75a26222 100644 >--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi >+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi >@@ -5,6 +5,7 @@ > > #include <dt-bindings/clock/imx8-clock.h> > #include <dt-bindings/dma/fsl-edma.h> >+#include <dt-bindings/clock/imx8-lpcg.h> > #include <dt-bindings/firmware/imx/rsrc.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> >@@ -231,6 +232,7 @@ xtal24m: clock-xtal24m { > }; > > /* sorted in register address */ >+ #include "imx8-ss-cm40.dtsi" > #include "imx8-ss-adma.dtsi" > #include "imx8-ss-conn.dtsi" > #include "imx8-ss-ddr.dtsi" >diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi >index 10e16d84c0c3b..0313f295de2e9 100644 >--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi >+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi >@@ -317,6 +317,7 @@ map0 { > /* sorted in register address */ > #include "imx8-ss-img.dtsi" > #include "imx8-ss-vpu.dtsi" >+ #include "imx8-ss-cm40.dtsi" > #include "imx8-ss-gpu0.dtsi" > #include "imx8-ss-adma.dtsi" > #include "imx8-ss-conn.dtsi" > >-- >2.34.1 > --
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi new file mode 100644 index 0000000000000..10a05db06ade9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +cm40_ipg_clk: clock-cm40-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm40_ipg_clk"; +}; + +cm40_subsys: bus@34000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x34000000 0x0 0x34000000 0x4000000>; + interrupt-parent = <&cm40_intmux>; + + cm40_i2c: i2c@37230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x37230000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cm40_i2c_lpcg IMX_LPCG_CLK_0>, + <&cm40_i2c_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + status = "disabled"; + }; + + cm40_intmux: intmux@37400000 { + compatible = "fsl,imx-intmux"; + reg = <0x37400000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&cm40_ipg_clk>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; + status = "disabled"; + }; + + cm40_i2c_lpcg: clock-controller@37630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x37630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>, + <&cm40_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "cm40_lpcg_i2c_clk", + "cm40_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index a0674c5c55766..9d49c75a26222 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/clock/imx8-clock.h> #include <dt-bindings/dma/fsl-edma.h> +#include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -231,6 +232,7 @@ xtal24m: clock-xtal24m { }; /* sorted in register address */ + #include "imx8-ss-cm40.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 10e16d84c0c3b..0313f295de2e9 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -317,6 +317,7 @@ map0 { /* sorted in register address */ #include "imx8-ss-img.dtsi" #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-cm40.dtsi" #include "imx8-ss-gpu0.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi"