| Message ID | 20240329205904.25002-1-ddrokosov@salutedevices.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver | expand |
On Fri, Mar 29, 2024 at 11:58:43PM +0300, Dmitry Rokosov wrote: > The 'sys_pll_div16' input clock is used as one of the sources for the > GEN clock. > > Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> > --- > .../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > index 6d84cee1bd75..f6668991ff1f 100644 > --- a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > @@ -29,6 +29,7 @@ properties: > - description: input fixed pll div5 > - description: input fixed pll div7 > - description: input hifi pll > + - description: input sys pll div16 > - description: input oscillator (usually at 24MHz) > > clock-names: > @@ -38,6 +39,7 @@ properties: > - const: fclk_div5 > - const: fclk_div7 > - const: hifi_pll > + - const: sys_pll_div16 > - const: xtal And adding an entry in the middle is also an ABI break. New entries go on the end (and should be optional).
On Fri, 29 Mar 2024 23:58:45 +0300, Dmitry Rokosov wrote: > Add the documentation and dt bindings for Amlogic A1 CPU clock > controller. > > This controller consists of the general 'cpu_clk' and two main parents: > 'cpu fixed clock' and 'syspll'. The 'cpu fixed clock' is an internal > fixed clock, while the 'syspll' serves as an external input from the A1 > PLL clock controller. > > Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> > --- > .../bindings/clock/amlogic,a1-cpu-clkc.yaml | 64 +++++++++++++++++++ > .../dt-bindings/clock/amlogic,a1-cpu-clkc.h | 19 ++++++ > 2 files changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-cpu-clkc.yaml > create mode 100644 include/dt-bindings/clock/amlogic,a1-cpu-clkc.h > Reviewed-by: Rob Herring <robh@kernel.org>
Hello Rob, Thank you for the quick review. On Mon, Apr 01, 2024 at 09:21:36AM -0500, Rob Herring wrote: > On Fri, Mar 29, 2024 at 11:58:43PM +0300, Dmitry Rokosov wrote: > > The 'sys_pll_div16' input clock is used as one of the sources for the > > GEN clock. > > > > Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> > > --- > > .../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 5 ++++- > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > > index 6d84cee1bd75..f6668991ff1f 100644 > > --- a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > > @@ -29,6 +29,7 @@ properties: > > - description: input fixed pll div5 > > - description: input fixed pll div7 > > - description: input hifi pll > > + - description: input sys pll div16 > > - description: input oscillator (usually at 24MHz) > > > > clock-names: > > @@ -38,6 +39,7 @@ properties: > > - const: fclk_div5 > > - const: fclk_div7 > > - const: hifi_pll > > + - const: sys_pll_div16 > > - const: xtal > > And adding an entry in the middle is also an ABI break. New entries go > on the end (and should be optional). The clock source sys_pll_div16, being one of the GEN clock parents, plays a crucial role and cannot be tagged as "optional". Unfortunately, it was not implemented earlier due to the cpu clock ctrl driver's pending status on the TODO list. I would greatly appreciate your advice on the best and simplest way to resolve this matter in an effective manner..
The CPU clock controller plays a general role in the Amlogic A1 SoC family by generating CPU clocks. As an APB slave module, it offers the capability to inherit the CPU clock from two sources: the internal fixed clock known as 'cpu fixed clock' and the external input provided by the A1 PLL clock controller, referred to as 'syspll'. It is important for the driver to handle the cpu_clk rate switching effectively by transitioning to the CPU fixed clock to avoid any potential execution freezes. Validation: * to double-check all clk flags, run the below helper script: ``` pushd /sys/kernel/debug/clk for f in *; do if [[ -f "$f/clk_flags" ]]; then flags="$(cat $f/clk_flags | awk '{$1=$1};1' | sed ':a;N;$!ba;s/\n/ | /g')" echo -e "$f: $flags" fi done popd ``` * to trace the current clks state, use the '/sys/kernel/debug/clk/clk_dump' node with jq post-processing: ``` $ cat /sys/kernel/debug/clk/clk_dump | jq '.' > clk_dump.json ``` * to see the CPU clock hierarchy, use the '/sys/kernel/debug/clk/clk_summary' node with jq post-processing: ``` $ cat /sys/kernel/debug/clk/clk_summary | jq '.' > clk_dump.json ``` when cpu_clk is inherited from sys_pll, it should be: ``` syspll_in 1 1 0 24000000 0 0 50000 Y deviceless no_connection_id sys_pll 2 2 0 1200000000 0 0 50000 Y deviceless no_connection_id cpu_clk 1 1 0 1200000000 0 0 50000 Y cpu0 no_connection_id cpu0 no_connection_id fd000000.clock-controller dvfs deviceless no_connection_id ``` and from cpu fixed clock: ``` fclk_div3_div 1 1 0 512000000 0 0 50000 Y deviceless no_connection_id fclk_div3 4 4 0 512000000 0 0 50000 Y deviceless no_connection_id cpu_fsource_sel0 1 1 0 512000000 0 0 50000 Y deviceless no_connection_id cpu_fsource_div0 1 1 0 128000000 0 0 50000 Y deviceless no_connection_id cpu_fsel0 1 1 0 128000000 0 0 50000 Y deviceless no_connection_id cpu_fclk 1 1 0 128000000 0 0 50000 Y deviceless no_connection_id cpu_clk 1 1 0 128000000 0 0 50000 Y cpu0 no_connection_id cpu0 no_connection_id fd000000.clock-controller dvfs deviceless no_connection_id ``` * to debug cpu clk rate propagation and proper parent switching, compile kernel with the following definition: $ sed -i "s/undef CLOCK_ALLOW_WRITE_DEBUGFS/define CLOCK_ALLOW_WRITE_DEBUGFS/g" drivers/clk/clk.c after that, clk_rate debug node for each clock will be available for write operation Dmitry Rokosov (6): dt-bindings: clock: meson: a1: pll: introduce new syspll bindings clk: meson: a1: pll: support 'syspll' general-purpose PLL for CPU clock dt-bindings: clock: meson: a1: peripherals: support sys_pll_div16 input clk: meson: a1: peripherals: support 'sys_pll_div16' clock as GEN input dt-bindings: clock: meson: add A1 CPU clock controller bindings clk: meson: a1: add Amlogic A1 CPU clock controller driver .../bindings/clock/amlogic,a1-cpu-clkc.yaml | 64 ++++ .../clock/amlogic,a1-peripherals-clkc.yaml | 5 +- .../bindings/clock/amlogic,a1-pll-clkc.yaml | 7 +- drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a1-cpu.c | 324 ++++++++++++++++++ drivers/clk/meson/a1-cpu.h | 16 + drivers/clk/meson/a1-peripherals.c | 4 +- drivers/clk/meson/a1-pll.c | 78 +++++ drivers/clk/meson/a1-pll.h | 6 + .../dt-bindings/clock/amlogic,a1-cpu-clkc.h | 19 + .../dt-bindings/clock/amlogic,a1-pll-clkc.h | 2 + 12 files changed, 531 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-cpu-clkc.yaml create mode 100644 drivers/clk/meson/a1-cpu.c create mode 100644 drivers/clk/meson/a1-cpu.h create mode 100644 include/dt-bindings/clock/amlogic,a1-cpu-clkc.h