| Message ID | 20240403112253.1432390-16-balasubramani.vivekanandan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable dislay support for Battlemage | expand |
On Wed, 03 Apr 2024, Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> wrote: > From: Clint Taylor <clinton.a.taylor@intel.com> > > Write both CX0 Lanes for Context Toggle for all except TC pin assignment D. Seems like a fix that should be the first patch in the series, no? > BSPEC: 64539 The spelling is "Bspec". > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> > Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 20035be015c3..cbcb6651dfed 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2558,7 +2558,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, > { > const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20; > bool dp = false; > - int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; > + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); > u32 clock = crtc_state->port_clock; > bool cntx; > int i; > @@ -2634,19 +2634,19 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, > } > > /* 4. Program custom width to match the link protocol */ > - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_WIDTH, > + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH, > PHY_C20_CUSTOM_WIDTH_MASK, > PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)), > MB_WRITE_COMMITTED); > > /* 5. For DP or 6. For HDMI */ > if (dp) { > - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, > + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, > BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, > BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)), > MB_WRITE_COMMITTED); > } else { > - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, > + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, > BIT(7) | PHY_C20_CUSTOM_SERDES_MASK, > is_hdmi_frl(clock) ? BIT(7) : 0, > MB_WRITE_COMMITTED); > @@ -2660,7 +2660,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, > * 7. Write Vendor specific registers to toggle context setting to load > * the updated programming toggle context bit > */ > - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, > + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, > BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); > }
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 20035be015c3..cbcb6651dfed 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2558,7 +2558,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, { const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20; bool dp = false; - int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); u32 clock = crtc_state->port_clock; bool cntx; int i; @@ -2634,19 +2634,19 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, } /* 4. Program custom width to match the link protocol */ - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_WIDTH, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH, PHY_C20_CUSTOM_WIDTH_MASK, PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)), MB_WRITE_COMMITTED); /* 5. For DP or 6. For HDMI */ if (dp) { - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)), MB_WRITE_COMMITTED); } else { - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(7) | PHY_C20_CUSTOM_SERDES_MASK, is_hdmi_frl(clock) ? BIT(7) : 0, MB_WRITE_COMMITTED); @@ -2660,7 +2660,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, * 7. Write Vendor specific registers to toggle context setting to load * the updated programming toggle context bit */ - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); }