| Message ID | 20240328095044.2926125-6-quic_sibis@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | qcom: x1e80100: Enable CPUFreq | expand |
On Thu, Mar 28, 2024 at 03:20:44PM +0530, Sibi Sankar wrote: > Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node. > > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 27 ++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 4e0ec859ed61..d1d232cd1f25 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -68,6 +68,7 @@ CPU0: cpu@0 { > compatible = "qcom,oryon"; > reg = <0x0 0x0>; > enable-method = "psci"; > + clocks = <&scmi_dvfs 0>; > next-level-cache = <&L2_0>; > power-domains = <&CPU_PD0>; > power-domain-names = "psci"; Any reason why you wouldn't want to use the new genpd based perf controls. IIRC it was added based on mainly Qcom platform requirements. - clocks = <&scmi_dvfs 0>; next-level-cache = <&L2_0>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; + power-domains = <&CPU_PD0>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; And the associated changes in the scmi dvfs node for cells property. This change is OK but just wanted to check the reasoning for the choice. -- Regards, Sudeep
On Tue, 2 Apr 2024 at 13:10, Sudeep Holla <sudeep.holla@arm.com> wrote: > > On Thu, Mar 28, 2024 at 03:20:44PM +0530, Sibi Sankar wrote: > > Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node. > > > > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 27 ++++++++++++++++++++++++++ > > 1 file changed, 27 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > index 4e0ec859ed61..d1d232cd1f25 100644 > > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > @@ -68,6 +68,7 @@ CPU0: cpu@0 { > > compatible = "qcom,oryon"; > > reg = <0x0 0x0>; > > enable-method = "psci"; > > + clocks = <&scmi_dvfs 0>; > > next-level-cache = <&L2_0>; > > power-domains = <&CPU_PD0>; > > power-domain-names = "psci"; > > > Any reason why you wouldn't want to use the new genpd based perf controls. > IIRC it was added based on mainly Qcom platform requirements. > > - clocks = <&scmi_dvfs 0>; > next-level-cache = <&L2_0>; > - power-domains = <&CPU_PD0>; > - power-domain-names = "psci"; > + power-domains = <&CPU_PD0>, <&scmi_dvfs 0>; > + power-domain-names = "psci", "perf"; > > > And the associated changes in the scmi dvfs node for cells property. > > This change is OK but just wanted to check the reasoning for the choice. To me, it seems reasonable to move to the new binding with #power-domain-cells for protocol@13. This becomes more future proof, as it can then easily be extended to be used beyond CPUs. That said, I just submitted a patch [1] to update the examples in the scmi DT doc to use #power-domain-cells in favor of #clock-cells. I don't know if there is a better way to promote the new bindings? Perhaps moving Juno to use this too? Kind regards Uffe [1] https://lore.kernel.org/all/20240403111106.1110940-1-ulf.hansson@linaro.org/
On 4/3/24 16:50, Ulf Hansson wrote: > On Tue, 2 Apr 2024 at 13:10, Sudeep Holla <sudeep.holla@arm.com> wrote: >> >> On Thu, Mar 28, 2024 at 03:20:44PM +0530, Sibi Sankar wrote: >>> Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node. >>> >>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 27 ++++++++++++++++++++++++++ >>> 1 file changed, 27 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> index 4e0ec859ed61..d1d232cd1f25 100644 >>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> @@ -68,6 +68,7 @@ CPU0: cpu@0 { >>> compatible = "qcom,oryon"; >>> reg = <0x0 0x0>; >>> enable-method = "psci"; >>> + clocks = <&scmi_dvfs 0>; >>> next-level-cache = <&L2_0>; >>> power-domains = <&CPU_PD0>; >>> power-domain-names = "psci"; >> >> >> Any reason why you wouldn't want to use the new genpd based perf controls. >> IIRC it was added based on mainly Qcom platform requirements. >> >> - clocks = <&scmi_dvfs 0>; >> next-level-cache = <&L2_0>; >> - power-domains = <&CPU_PD0>; >> - power-domain-names = "psci"; >> + power-domains = <&CPU_PD0>, <&scmi_dvfs 0>; >> + power-domain-names = "psci", "perf"; >> >> >> And the associated changes in the scmi dvfs node for cells property. >> >> This change is OK but just wanted to check the reasoning for the choice. > > To me, it seems reasonable to move to the new binding with > #power-domain-cells for protocol@13. This becomes more future proof, > as it can then easily be extended to be used beyond CPUs. > > That said, I just submitted a patch [1] to update the examples in the > scmi DT doc to use #power-domain-cells in favor of #clock-cells. I > don't know if there is a better way to promote the new bindings? > Perhaps moving Juno to use this too? > > Kind regards > Uffe Sudeep/Ulfe, Thanks I'll move to the new recommendation. -Sibi > > [1] > https://lore.kernel.org/all/20240403111106.1110940-1-ulf.hansson@linaro.org/
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 4e0ec859ed61..d1d232cd1f25 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -68,6 +68,7 @@ CPU0: cpu@0 { compatible = "qcom,oryon"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&scmi_dvfs 0>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; @@ -85,6 +86,7 @@ CPU1: cpu@100 { compatible = "qcom,oryon"; reg = <0x0 0x100>; enable-method = "psci"; + clocks = <&scmi_dvfs 0>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; @@ -96,6 +98,7 @@ CPU2: cpu@200 { compatible = "qcom,oryon"; reg = <0x0 0x200>; enable-method = "psci"; + clocks = <&scmi_dvfs 0>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; @@ -107,6 +110,7 @@ CPU3: cpu@300 { compatible = "qcom,oryon"; reg = <0x0 0x300>; enable-method = "psci"; + clocks = <&scmi_dvfs 0>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; @@ -118,6 +122,7 @@ CPU4: cpu@10000 { compatible = "qcom,oryon"; reg = <0x0 0x10000>; enable-method = "psci"; + clocks = <&scmi_dvfs 1>; next-level-cache = <&L2_1>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; @@ -135,6 +140,7 @@ CPU5: cpu@10100 { compatible = "qcom,oryon"; reg = <0x0 0x10100>; enable-method = "psci"; + clocks = <&scmi_dvfs 1>; next-level-cache = <&L2_1>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; @@ -146,6 +152,7 @@ CPU6: cpu@10200 { compatible = "qcom,oryon"; reg = <0x0 0x10200>; enable-method = "psci"; + clocks = <&scmi_dvfs 1>; next-level-cache = <&L2_1>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; @@ -157,6 +164,7 @@ CPU7: cpu@10300 { compatible = "qcom,oryon"; reg = <0x0 0x10300>; enable-method = "psci"; + clocks = <&scmi_dvfs 1>; next-level-cache = <&L2_1>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; @@ -168,6 +176,7 @@ CPU8: cpu@20000 { compatible = "qcom,oryon"; reg = <0x0 0x20000>; enable-method = "psci"; + clocks = <&scmi_dvfs 2>; next-level-cache = <&L2_2>; power-domains = <&CPU_PD8>; power-domain-names = "psci"; @@ -185,6 +194,7 @@ CPU9: cpu@20100 { compatible = "qcom,oryon"; reg = <0x0 0x20100>; enable-method = "psci"; + clocks = <&scmi_dvfs 2>; next-level-cache = <&L2_2>; power-domains = <&CPU_PD9>; power-domain-names = "psci"; @@ -196,6 +206,7 @@ CPU10: cpu@20200 { compatible = "qcom,oryon"; reg = <0x0 0x20200>; enable-method = "psci"; + clocks = <&scmi_dvfs 2>; next-level-cache = <&L2_2>; power-domains = <&CPU_PD10>; power-domain-names = "psci"; @@ -207,6 +218,7 @@ CPU11: cpu@20300 { compatible = "qcom,oryon"; reg = <0x0 0x20300>; enable-method = "psci"; + clocks = <&scmi_dvfs 2>; next-level-cache = <&L2_2>; power-domains = <&CPU_PD11>; power-domain-names = "psci"; @@ -309,6 +321,21 @@ scm: scm { interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; + + scmi { + compatible = "arm,scmi"; + mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + }; }; clk_virt: interconnect-0 {
Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)