| Message ID | 20240404-rk3588-pcie-bifurcation-fixes-v1-2-9907136eeafd@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RK3588 PCIe bifurcation fixes | expand |
Am Donnerstag, 4. April 2024, 19:11:27 CEST schrieb Sebastian Reichel: > From: Sebastian Reichel <sebastian.reichel@collabora.com> > > Currently the PCIe v3 PHY driver only sets the pcie1ln_sel bits, but > does not clear them because of an incorrect write mask. This fixes up > the issue by using a newly introduced constant for the write mask. > > While at it also introduces a proper GENMASK based constant for the > PCIE30_PHY_MODE. > > Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3") > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> after checking with the soc manual Reviewed-by: Heiko Stuebner <heiko@sntech.de>
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c index d5bcc9c42b28..9857ee45b89e 100644 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -40,6 +40,8 @@ #define RK3588_BIFURCATION_LANE_0_1 BIT(0) #define RK3588_BIFURCATION_LANE_2_3 BIT(1) #define RK3588_LANE_AGGREGATION BIT(2) +#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16) +#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16) struct rockchip_p3phy_ops; @@ -149,14 +151,15 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) } reg = mode; - regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, + RK3588_PCIE30_PHY_MODE_EN | reg); /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ if (!IS_ERR(priv->pipe_grf)) { - reg = mode & 3; + reg = mode & (RK3588_BIFURCATION_LANE_0_1 | RK3588_BIFURCATION_LANE_2_3); if (reg) regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, - (reg << 16) | reg); + RK3588_PCIE1LN_SEL_EN | reg); } reset_control_deassert(priv->p30phy);