| Message ID | 20240404122559.898930-13-peter.griffin@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | HSI2, UFS & UFS phy support for Tensor GS101 | expand |
On 04/04/2024 14:25, Peter Griffin wrote: > This option is intended to be set on platforms whose ufspr > registers are only accessible via smc call (such as gs101). > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 04/04/2024, Peter Griffin wrote: > This option is intended to be set on platforms whose ufspr > registers are only accessible via smc call (such as gs101). > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- Tested-by: Will McVicker <willmcvicker@google.com> I tested this patch series on a Pixel 6 device. I was able to successfully mount two of the Android ext4 partitions -- efs and metadata. root@google-gs:~# mount | grep /dev/sda /dev/sda5 on /mnt/efs type ext4 (rw,relatime) /dev/sda8 on /mnt/metadata type ext4 (rw,relatime) Regards, Will
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 734d40f99e31..7b68229f6264 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -1186,7 +1186,9 @@ static int exynos_ufs_init(struct ufs_hba *hba) if (ret) goto out; exynos_ufs_specify_phy_time_attr(ufs); - exynos_ufs_config_smu(ufs); + + if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) + exynos_ufs_config_smu(ufs); return 0; out: diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index a4bd6646d7f1..0fc21b6bbfcd 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -221,6 +221,7 @@ struct exynos_ufs { #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3) #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4) #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5) +#define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6) }; #define for_each_ufs_rx_lane(ufs, i) \
This option is intended to be set on platforms whose ufspr registers are only accessible via smc call (such as gs101). Signed-off-by: Peter Griffin <peter.griffin@linaro.org> --- drivers/ufs/host/ufs-exynos.c | 4 +++- drivers/ufs/host/ufs-exynos.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-)