| Message ID | 20240408124005.182565-1-amadeus@jmu.edu.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/1] arm64: dts: rockchip: enable onboard spi flash for rock-3a | expand |
Hi Chukun, On 2024-04-08 14:40, Chukun Pan wrote: > There is a mx25u12835f spi flash on this board, enable it. > > [ 2.525805] spi-nor spi4.0: mx25u12835f (16384 Kbytes) > > Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> > --- > arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts > index a5e974ea659e..d8738cc47c73 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts > @@ -757,6 +757,18 @@ &sdmmc2 { > status = "okay"; > }; > > +&sfc { This is missing: #address-cells = <1>; #size-cells = <0>; > + status = "okay"; > + > + flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0x0>; > + spi-max-frequency = <50000000>; At least in U-Boot the spi clock only support 24, 100 or 200 mhz and I am pretty sure the spi flash support 100mhz, so I would suggest you test with 100mhz, same as used on other rk356x boards. For U-Boot I have used 24 mhz for rk356x boards not defining a flash@0 node in linux device tree, such as the rock-3a board. Regards, Jonas > + spi-rx-bus-width = <4>; > + spi-tx-bus-width = <1>; > + }; > +}; > + > &tsadc { > rockchip,hw-tshut-mode = <1>; > rockchip,hw-tshut-polarity = <0>;
Hi again, On 2024-04-08 16:44, Jonas Karlman wrote: > Hi Chukun, > > On 2024-04-08 14:40, Chukun Pan wrote: >> There is a mx25u12835f spi flash on this board, enable it. >> >> [ 2.525805] spi-nor spi4.0: mx25u12835f (16384 Kbytes) >> >> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> >> --- >> arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts >> index a5e974ea659e..d8738cc47c73 100644 >> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts >> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts >> @@ -757,6 +757,18 @@ &sdmmc2 { >> status = "okay"; >> }; >> >> +&sfc { > > This is missing: > > #address-cells = <1>; > #size-cells = <0>; > >> + status = "okay"; >> + >> + flash@0 { >> + compatible = "jedec,spi-nor"; >> + reg = <0x0>; >> + spi-max-frequency = <50000000>; > > At least in U-Boot the spi clock only support 24, 100 or 200 mhz and I > am pretty sure the spi flash support 100mhz, so I would suggest you test > with 100mhz, same as used on other rk356x boards. Sorry, looked at spi clock instead of sfc clock. sfc clock support 24, 50, 75, 100, 125 and 150 mhz. Regards, Jonas > > For U-Boot I have used 24 mhz for rk356x boards not defining a flash@0 > node in linux device tree, such as the rock-3a board. > > Regards, > Jonas > >> + spi-rx-bus-width = <4>; >> + spi-tx-bus-width = <1>; >> + }; >> +}; >> + >> &tsadc { >> rockchip,hw-tshut-mode = <1>; >> rockchip,hw-tshut-polarity = <0>; >
Am Montag, 8. April 2024, 16:56:59 CEST schrieb Jonas Karlman: > On 2024-04-08 16:44, Jonas Karlman wrote: > > On 2024-04-08 14:40, Chukun Pan wrote: > >> There is a mx25u12835f spi flash on this board, enable it. > >> > >> [ 2.525805] spi-nor spi4.0: mx25u12835f (16384 Kbytes) > >> > >> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> > >> --- > >> arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 12 ++++++++++++ > >> 1 file changed, 12 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts > >> index a5e974ea659e..d8738cc47c73 100644 > >> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts > >> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts > >> @@ -757,6 +757,18 @@ &sdmmc2 { > >> status = "okay"; > >> }; > >> > >> +&sfc { > > > > This is missing: > > > > #address-cells = <1>; > > #size-cells = <0>; > > > >> + status = "okay"; > >> + > >> + flash@0 { > >> + compatible = "jedec,spi-nor"; > >> + reg = <0x0>; > >> + spi-max-frequency = <50000000>; > > > > At least in U-Boot the spi clock only support 24, 100 or 200 mhz and I > > am pretty sure the spi flash support 100mhz, so I would suggest you test > > with 100mhz, same as used on other rk356x boards. > > Sorry, looked at spi clock instead of sfc clock. > sfc clock support 24, 50, 75, 100, 125 and 150 mhz. I think in some previous discussion the agreement was that the node should specify the max frequency the flash supports and have the controller worry about its own clock ranges. Though in this case the 50MHz for the flash even matches the clock frequency supported by the sfc
On 2024-04-08 17:04, Heiko Stübner wrote: > Am Montag, 8. April 2024, 16:56:59 CEST schrieb Jonas Karlman: >> On 2024-04-08 16:44, Jonas Karlman wrote: >>> On 2024-04-08 14:40, Chukun Pan wrote: >>>> There is a mx25u12835f spi flash on this board, enable it. >>>> >>>> [ 2.525805] spi-nor spi4.0: mx25u12835f (16384 Kbytes) >>>> >>>> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> >>>> --- >>>> arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 12 ++++++++++++ >>>> 1 file changed, 12 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts >>>> index a5e974ea659e..d8738cc47c73 100644 >>>> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts >>>> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts >>>> @@ -757,6 +757,18 @@ &sdmmc2 { >>>> status = "okay"; >>>> }; >>>> >>>> +&sfc { >>> >>> This is missing: >>> >>> #address-cells = <1>; >>> #size-cells = <0>; >>> >>>> + status = "okay"; >>>> + >>>> + flash@0 { >>>> + compatible = "jedec,spi-nor"; >>>> + reg = <0x0>; >>>> + spi-max-frequency = <50000000>; >>> >>> At least in U-Boot the spi clock only support 24, 100 or 200 mhz and I >>> am pretty sure the spi flash support 100mhz, so I would suggest you test >>> with 100mhz, same as used on other rk356x boards. >> >> Sorry, looked at spi clock instead of sfc clock. >> sfc clock support 24, 50, 75, 100, 125 and 150 mhz. > > I think in some previous discussion the agreement was that the node > should specify the max frequency the flash supports and have the > controller worry about its own clock ranges. Interesting, sounds like there is a need to do some modification to spi and clk drivers in U-Boot to support that. > > Though in this case the 50MHz for the flash even matches the clock > frequency supported by the sfc I think the on-board spi nor flash support 104/108/133 mhz so 50 mhz is wrong in any case. Regards, Jonas > >
> I think the on-board spi nor flash support 104/108/133 mhz > so 50 mhz is wrong in any case. Thanks, I tested 104MHz on linux and it works fine. As for 133 MHz, only MX25U12835FZNI-08G supports it. And I didn't find it support 108MHz in the datasheet of MX25U12835F. Thanks, Chukun
On Mon, 08 Apr 2024 20:40:05 +0800, Chukun Pan wrote: > There is a mx25u12835f spi flash on this board, enable it. > > [ 2.525805] spi-nor spi4.0: mx25u12835f (16384 Kbytes) > > Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> > --- > arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y rockchip/rk3568-rock-3a.dtb' for 20240408124005.182565-1-amadeus@jmu.edu.cn: arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts:765.3-15: Warning (reg_format): /spi@fe300000/flash@0:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm64/boot/dts/rockchip/rk356x.dtsi:1091.20-1100.4: Warning (spi_bus_bridge): /spi@fe300000: incorrect #address-cells for SPI bus also defined at arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts:760.6-770.3 arch/arm64/boot/dts/rockchip/rk356x.dtsi:1091.20-1100.4: Warning (spi_bus_bridge): /spi@fe300000: incorrect #size-cells for SPI bus also defined at arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts:760.6-770.3 arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dtb: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge' arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts:763.10-769.4: Warning (avoid_default_addr_size): /spi@fe300000/flash@0: Relying on default #address-cells value arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts:763.10-769.4: Warning (avoid_default_addr_size): /spi@fe300000/flash@0: Relying on default #size-cells value
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index a5e974ea659e..d8738cc47c73 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -757,6 +757,18 @@ &sdmmc2 { status = "okay"; }; +&sfc { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &tsadc { rockchip,hw-tshut-mode = <1>; rockchip,hw-tshut-polarity = <0>;
There is a mx25u12835f spi flash on this board, enable it. [ 2.525805] spi-nor spi4.0: mx25u12835f (16384 Kbytes) Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> --- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)