| Message ID | 20240404122559.898930-14-peter.griffin@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 9238cad67969e7001e296eaedcdffc63fc38ab30 |
| Headers | show |
| Series | HSI2, UFS & UFS phy support for Tensor GS101 | expand |
On 04/04/2024 14:25, Peter Griffin wrote: > This option is intended to be set for SoCs that have HCI_V2P1_CTRL > register and can select their tick source via IA_TICK_SEL bit. > > Source clock selection for timer tick > 0x0 = Bus clock (aclk) > 0x1 = Function clock (mclk) > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 04/04/2024, Peter Griffin wrote: > This option is intended to be set for SoCs that have HCI_V2P1_CTRL > register and can select their tick source via IA_TICK_SEL bit. > > Source clock selection for timer tick > 0x0 = Bus clock (aclk) > 0x1 = Function clock (mclk) > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > --- Tested-by: Will McVicker <willmcvicker@google.com> I tested this patch series on a Pixel 6 device. I was able to successfully mount two of the Android ext4 partitions -- efs and metadata. root@google-gs:~# mount | grep /dev/sda /dev/sda5 on /mnt/efs type ext4 (rw,relatime) /dev/sda8 on /mnt/metadata type ext4 (rw,relatime) Regards, Will
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 7b68229f6264..1bfda9c75703 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -50,6 +50,8 @@ #define HCI_ERR_EN_N_LAYER 0x80 #define HCI_ERR_EN_T_LAYER 0x84 #define HCI_ERR_EN_DME_LAYER 0x88 +#define HCI_V2P1_CTRL 0x8C +#define IA_TICK_SEL BIT(16) #define HCI_CLKSTOP_CTRL 0xB0 #define REFCLKOUT_STOP BIT(4) #define MPHY_APBCLK_STOP BIT(3) @@ -1005,6 +1007,13 @@ static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs) { u32 val; + /* Select function clock (mclk) for timer tick */ + if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) { + val = hci_readl(ufs, HCI_V2P1_CTRL); + val |= IA_TICK_SEL; + hci_writel(ufs, val, HCI_V2P1_CTRL); + } + val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL); hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL); } diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index 0fc21b6bbfcd..acf07cc54684 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -222,6 +222,7 @@ struct exynos_ufs { #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4) #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5) #define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6) +#define EXYNOS_UFS_OPT_TIMER_TICK_SELECT BIT(7) }; #define for_each_ufs_rx_lane(ufs, i) \
This option is intended to be set for SoCs that have HCI_V2P1_CTRL register and can select their tick source via IA_TICK_SEL bit. Source clock selection for timer tick 0x0 = Bus clock (aclk) 0x1 = Function clock (mclk) Signed-off-by: Peter Griffin <peter.griffin@linaro.org> --- drivers/ufs/host/ufs-exynos.c | 9 +++++++++ drivers/ufs/host/ufs-exynos.h | 1 + 2 files changed, 10 insertions(+)