| Message ID | 20240410004832.3726922-4-yoshihiro.shimoda.uh@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | PCI: rcar-gen4: Add R-Car V4H support | expand |
On Wed, Apr 10, 2024 at 09:48:28AM +0900, Yoshihiro Shimoda wrote: > R-Car Gen4 PCIe controller needs to use the Synopsys-specific PCIe > configuration registers. So, add the macros. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 26dae4837462..aa4db6eaf02a 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -71,6 +71,9 @@ > #define LINK_WAIT_IATU 9 > > /* Synopsys-specific PCIe configuration registers */ > +#define PCIE_PORT_FORCE 0x708 > +#define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) > + > #define PCIE_PORT_AFR 0x70C > #define PORT_AFR_N_FTS_MASK GENMASK(15, 8) > #define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n) > @@ -92,6 +95,9 @@ > #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) > #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) > > +#define PCIE_PORT_LANE_SKEW 0x714 > +#define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) > + > #define PCIE_PORT_DEBUG0 0x728 > #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f > #define PORT_LOGIC_LTSSM_STATE_L0 0x11 > -- > 2.25.1 > >
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 26dae4837462..aa4db6eaf02a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -71,6 +71,9 @@ #define LINK_WAIT_IATU 9 /* Synopsys-specific PCIe configuration registers */ +#define PCIE_PORT_FORCE 0x708 +#define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) + #define PCIE_PORT_AFR 0x70C #define PORT_AFR_N_FTS_MASK GENMASK(15, 8) #define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n) @@ -92,6 +95,9 @@ #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) +#define PCIE_PORT_LANE_SKEW 0x714 +#define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) + #define PCIE_PORT_DEBUG0 0x728 #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f #define PORT_LOGIC_LTSSM_STATE_L0 0x11
R-Car Gen4 PCIe controller needs to use the Synopsys-specific PCIe configuration registers. So, add the macros. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++ 1 file changed, 6 insertions(+)