[v9,0/6] riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs

Message ID	IA1PR20MB4953512A4DCAF293D7B1CBC2BB262@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive)
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Inochi Amaoto <inochiama@outlook.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Chao Wei <chao.wei@sophgo.com>, Chen Wang <unicorn_wang@outlook.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Inochi Amaoto <inochiama@outlook.com> Cc: Jisheng Zhang <jszhang@kernel.org>, Liu Gui <kenneth.liu@sophgo.com>, Jingbao Qiu <qiujingbao.dlmu@gmail.com>, dlan@gentoo.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v9 0/6] riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs Date: Sat, 9 Mar 2024 17:01:21 +0800 Message-ID: <IA1PR20MB4953512A4DCAF293D7B1CBC2BB262@IA1PR20MB4953.namprd20.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs \| expand [v9,0/6] riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs [v9,1/6] dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC [v9,2/6] clk: sophgo: Add clock support for CV1800 SoC [v9,3/6] clk: sophgo: Add clock support for CV1810 SoC [v9,4/6] clk: sophgo: Add clock support for SG2000 SoC [v9,5/6] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC [v9,6/6] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC

Inochi Amaoto March 9, 2024, 9:01 a.m. UTC

Add clock controller support for the Sophgo CV1800B, CV1812H and SG2000.

Changed from v8:
1. improve code.
2. remove default config in Kconfig.
3. merge patch 2-4 of v8 into one.

Changed from v7:
1. fix unused variables warnings in patch 3 of v7
2. fix wrong pointer type in patch 3 of v7
3. move the clk_disp_vip_parents variable to the patch 5 to avoid warning

Changed from v6:
1. fix dead lock when setting rate.
2. split the driver patch into several patch for easy reading.

Changed from v5:
1. rebased to mainline master tree
2. add SG2000 clock support.
3. fix document link

Changed from v4:
1. improve code for patch 2
2. remove the already applied bindings
https://lore.kernel.org/all/IA1PR20MB49535E448097F6FFC1218C39BB90A@IA1PR20MB4953.namprd20.prod.outlook.com/

Changed from v3:
1. improve comment of patch 3
2. cleanup the include of patch 2

Changed from v2:
1. remove clock-names from bindings.
2. remove clock-frequency node of DT from previous patch.
3. change some unused clock to bypass mode to avoid unlockable PLL.

Changed from v1:
1. fix license issues.

Inochi Amaoto (6):
  dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC
  clk: sophgo: Add clock support for CV1800 SoC
  clk: sophgo: Add clock support for CV1810 SoC
  clk: sophgo: Add clock support for SG2000 SoC
  riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC
  riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC

 .../bindings/clock/sophgo,cv1800-clk.yaml     |    3 +-
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi       |    4 +
 arch/riscv/boot/dts/sophgo/cv1812h.dtsi       |    4 +
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi        |   22 +-
 drivers/clk/Kconfig                           |    1 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/sophgo/Kconfig                    |   11 +
 drivers/clk/sophgo/Makefile                   |    7 +
 drivers/clk/sophgo/clk-cv1800.c               | 1537 +++++++++++++++++
 drivers/clk/sophgo/clk-cv1800.h               |  123 ++
 drivers/clk/sophgo/clk-cv18xx-common.c        |   66 +
 drivers/clk/sophgo/clk-cv18xx-common.h        |   81 +
 drivers/clk/sophgo/clk-cv18xx-ip.c            |  887 ++++++++++
 drivers/clk/sophgo/clk-cv18xx-ip.h            |  261 +++
 drivers/clk/sophgo/clk-cv18xx-pll.c           |  420 +++++
 drivers/clk/sophgo/clk-cv18xx-pll.h           |  118 ++
 16 files changed, 3540 insertions(+), 6 deletions(-)
 create mode 100644 drivers/clk/sophgo/Kconfig
 create mode 100644 drivers/clk/sophgo/Makefile
 create mode 100644 drivers/clk/sophgo/clk-cv1800.c
 create mode 100644 drivers/clk/sophgo/clk-cv1800.h
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.c
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.h
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.c
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.h
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.c
 create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.h

--
2.44.0

Inochi Amaoto March 15, 2024, 6:19 a.m. UTC | #1

Hi, Stephen,

Ping.

Do you still have some suggestion on this patch series?

On Sat, Mar 09, 2024 at 05:01:21PM +0800, Inochi Amaoto wrote:
> Add clock controller support for the Sophgo CV1800B, CV1812H and SG2000.
> 
> Changed from v8:
> 1. improve code.
> 2. remove default config in Kconfig.
> 3. merge patch 2-4 of v8 into one.
> 
> Changed from v7:
> 1. fix unused variables warnings in patch 3 of v7
> 2. fix wrong pointer type in patch 3 of v7
> 3. move the clk_disp_vip_parents variable to the patch 5 to avoid warning
> 
> Changed from v6:
> 1. fix dead lock when setting rate.
> 2. split the driver patch into several patch for easy reading.
> 
> Changed from v5:
> 1. rebased to mainline master tree
> 2. add SG2000 clock support.
> 3. fix document link
> 
> Changed from v4:
> 1. improve code for patch 2
> 2. remove the already applied bindings
> https://lore.kernel.org/all/IA1PR20MB49535E448097F6FFC1218C39BB90A@IA1PR20MB4953.namprd20.prod.outlook.com/
> 
> Changed from v3:
> 1. improve comment of patch 3
> 2. cleanup the include of patch 2
> 
> Changed from v2:
> 1. remove clock-names from bindings.
> 2. remove clock-frequency node of DT from previous patch.
> 3. change some unused clock to bypass mode to avoid unlockable PLL.
> 
> Changed from v1:
> 1. fix license issues.
> 
> Inochi Amaoto (6):
>   dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC
>   clk: sophgo: Add clock support for CV1800 SoC
>   clk: sophgo: Add clock support for CV1810 SoC
>   clk: sophgo: Add clock support for SG2000 SoC
>   riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC
>   riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC
> 
>  .../bindings/clock/sophgo,cv1800-clk.yaml     |    3 +-
>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi       |    4 +
>  arch/riscv/boot/dts/sophgo/cv1812h.dtsi       |    4 +
>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi        |   22 +-
>  drivers/clk/Kconfig                           |    1 +
>  drivers/clk/Makefile                          |    1 +
>  drivers/clk/sophgo/Kconfig                    |   11 +
>  drivers/clk/sophgo/Makefile                   |    7 +
>  drivers/clk/sophgo/clk-cv1800.c               | 1537 +++++++++++++++++
>  drivers/clk/sophgo/clk-cv1800.h               |  123 ++
>  drivers/clk/sophgo/clk-cv18xx-common.c        |   66 +
>  drivers/clk/sophgo/clk-cv18xx-common.h        |   81 +
>  drivers/clk/sophgo/clk-cv18xx-ip.c            |  887 ++++++++++
>  drivers/clk/sophgo/clk-cv18xx-ip.h            |  261 +++
>  drivers/clk/sophgo/clk-cv18xx-pll.c           |  420 +++++
>  drivers/clk/sophgo/clk-cv18xx-pll.h           |  118 ++
>  16 files changed, 3540 insertions(+), 6 deletions(-)
>  create mode 100644 drivers/clk/sophgo/Kconfig
>  create mode 100644 drivers/clk/sophgo/Makefile
>  create mode 100644 drivers/clk/sophgo/clk-cv1800.c
>  create mode 100644 drivers/clk/sophgo/clk-cv1800.h
>  create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.c
>  create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.h
>  create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.c
>  create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.h
>  create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.c
>  create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.h
> 
> --
> 2.44.0
>

Inochi Amaoto April 11, 2024, 7:38 a.m. UTC | #2

On Sat, 9 Mar 2024 17:01:21 +0800, Inochi Amaoto wrote:
> Add clock controller support for the Sophgo CV1800B, CV1812H and SG2000.
> 
> Changed from v8:
> 1. improve code.
> 2. remove default config in Kconfig.
> 3. merge patch 2-4 of v8 into one.
> 
> [...]

Applied to sophgo/for-next, thanks!

[5/6] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC
      https://github.com/sophgo/linux/commit/bb7b3419627eb34f3466022d1f4b3c942c09712d
[6/6] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC
      https://github.com/sophgo/linux/commit/18e8c6d2cced6c57d62813f49b57eeb8ee02f984

Thanks,
Inochi

Michael Opdenacker April 14, 2024, 5:56 a.m. UTC | #3

Hi Inochi

On 4/11/24 at 09:38, Inochi Amaoto wrote:
> On Sat, 9 Mar 2024 17:01:21 +0800, Inochi Amaoto wrote:
>> Add clock controller support for the Sophgo CV1800B, CV1812H and SG2000.
>>
>> Changed from v8:
>> 1. improve code.
>> 2. remove default config in Kconfig.
>> 3. merge patch 2-4 of v8 into one.
>>
>> [...]
> 
> Applied to sophgo/for-next, thanks!
> 
> [5/6] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC
>        https://github.com/sophgo/linux/commit/bb7b3419627eb34f3466022d1f4b3c942c09712d
> [6/6] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC
>        https://github.com/sophgo/linux/commit/18e8c6d2cced6c57d62813f49b57eeb8ee02f984

Oops, for your information, this last change
([6/6] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC) 
breaks my Milk-V Duo S board when I boot it with cv1812h-huashan-pi.dtb 
as I believe you suggested.

I don't know whether the board actually boots, but at least I don't get 
any more output in the console.

Has someone tested this on the real Huashan Pi board?

Cheers
Michael.

Inochi Amaoto April 14, 2024, 6:41 a.m. UTC | #4

On Sun, Apr 14, 2024 at 07:56:42AM +0200, Michael Opdenacker wrote:
> Hi Inochi
> 
> On 4/11/24 at 09:38, Inochi Amaoto wrote:
> > On Sat, 9 Mar 2024 17:01:21 +0800, Inochi Amaoto wrote:
> > > Add clock controller support for the Sophgo CV1800B, CV1812H and SG2000.
> > > 
> > > Changed from v8:
> > > 1. improve code.
> > > 2. remove default config in Kconfig.
> > > 3. merge patch 2-4 of v8 into one.
> > > 
> > > [...]
> > 
> > Applied to sophgo/for-next, thanks!
> > 
> > [5/6] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC
> >        https://github.com/sophgo/linux/commit/bb7b3419627eb34f3466022d1f4b3c942c09712d
> > [6/6] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC
> >        https://github.com/sophgo/linux/commit/18e8c6d2cced6c57d62813f49b57eeb8ee02f984
> 
> Oops, for your information, this last change
> ([6/6] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC)
> breaks my Milk-V Duo S board when I boot it with cv1812h-huashan-pi.dtb as I
> believe you suggested.
> 
> I don't know whether the board actually boots, but at least I don't get any
> more output in the console.
> 
> Has someone tested this on the real Huashan Pi board?
> 
> Cheers
> Michael.
> 

Hi Michael,

I think you boot with the `defconfig` config. This config does
not enable the CV1800 clk support. I think you may need to apply
[1], which enable the clk driver. Also if you want to test sdhci
with real clk, you can try [2]. I test them on the Milk-V Duo S.

Regards,
Inochi

[1] https://lore.kernel.org/all/IA1PR20MB4953CA5D46EA8913B130D502BB052@IA1PR20MB4953.namprd20.prod.outlook.com/
[2] https://lore.kernel.org/all/IA1PR20MB4953CA5D46EA8913B130D502BB052@IA1PR20MB4953.namprd20.prod.outlook.com/

Inochi Amaoto April 14, 2024, 6:43 a.m. UTC | #5

On Sun, Apr 14, 2024 at 02:41:21PM +0800, Inochi Amaoto wrote:
> On Sun, Apr 14, 2024 at 07:56:42AM +0200, Michael Opdenacker wrote:
> > Hi Inochi
> > 
> > On 4/11/24 at 09:38, Inochi Amaoto wrote:
> > > On Sat, 9 Mar 2024 17:01:21 +0800, Inochi Amaoto wrote:
> > > > Add clock controller support for the Sophgo CV1800B, CV1812H and SG2000.
> > > > 
> > > > Changed from v8:
> > > > 1. improve code.
> > > > 2. remove default config in Kconfig.
> > > > 3. merge patch 2-4 of v8 into one.
> > > > 
> > > > [...]
> > > 
> > > Applied to sophgo/for-next, thanks!
> > > 
> > > [5/6] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC
> > >        https://github.com/sophgo/linux/commit/bb7b3419627eb34f3466022d1f4b3c942c09712d
> > > [6/6] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC
> > >        https://github.com/sophgo/linux/commit/18e8c6d2cced6c57d62813f49b57eeb8ee02f984
> > 
> > Oops, for your information, this last change
> > ([6/6] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC)
> > breaks my Milk-V Duo S board when I boot it with cv1812h-huashan-pi.dtb as I
> > believe you suggested.
> > 
> > I don't know whether the board actually boots, but at least I don't get any
> > more output in the console.
> > 
> > Has someone tested this on the real Huashan Pi board?
> > 
> > Cheers
> > Michael.
> > 
> 
> Hi Michael,
> 
> I think you boot with the `defconfig` config. This config does
> not enable the CV1800 clk support. I think you may need to apply
> [1], which enable the clk driver. Also if you want to test sdhci
> with real clk, you can try [2]. I test them on the Milk-V Duo S.
> 
> Regards,
> Inochi
> 
> [1] https://lore.kernel.org/all/IA1PR20MB4953CA5D46EA8913B130D502BB052@IA1PR20MB4953.namprd20.prod.outlook.com/

I make a mistake when reordering the url.
[1] should be https://lore.kernel.org/all/IA1PR20MB49537E8B2D1FAAA7D5B8BDA2BB052@IA1PR20MB4953.namprd20.prod.outlook.com/

> [2] https://lore.kernel.org/all/IA1PR20MB4953CA5D46EA8913B130D502BB052@IA1PR20MB4953.namprd20.prod.outlook.com/

Michael Opdenacker April 14, 2024, 9:11 a.m. UTC | #6

Hi Inochi

Thanks for your help!

On 4/14/24 at 08:43, Inochi Amaoto wrote:
>> Hi Michael,
>>
>> I think you boot with the `defconfig` config. This config does
>> not enable the CV1800 clk support. I think you may need to apply
>> [1], which enable the clk driver. Also if you want to test sdhci
>> with real clk, you can try [2]. I test them on the Milk-V Duo S.
>>
>> Regards,
>> Inochi
>>
>> [1] https://lore.kernel.org/all/IA1PR20MB4953CA5D46EA8913B130D502BB052@IA1PR20MB4953.namprd20.prod.outlook.com/
> I make a mistake when reordering the url.
> [1] should be https://lore.kernel.org/all/IA1PR20MB49537E8B2D1FAAA7D5B8BDA2BB052@IA1PR20MB4953.namprd20.prod.outlook.com/

Indeed, I was using the "defconfig" config. Too used to having 
everything working with this configuration on RISC-V :-/

Gotcha for the CONFIG_CLK_SOPHGO_CV1800 setting. However, I'm confused. 
Why is this setting available in linux-next, but neither in 
git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git ("master" and 
"for-next") nor in github.com/sophgo/linux.git ("master" and "for-next") ?

What's the tree used to push to linux-next?

Cheers
Michael.

Inochi Amaoto April 14, 2024, 9:41 a.m. UTC | #7

On Sun, Apr 14, 2024 at 11:11:22AM +0200, Michael Opdenacker wrote:
> Hi Inochi
> 
> Thanks for your help!
> 
> On 4/14/24 at 08:43, Inochi Amaoto wrote:
> > > Hi Michael,
> > > 
> > > I think you boot with the `defconfig` config. This config does
> > > not enable the CV1800 clk support. I think you may need to apply
> > > [1], which enable the clk driver. Also if you want to test sdhci
> > > with real clk, you can try [2]. I test them on the Milk-V Duo S.
> > > 
> > > Regards,
> > > Inochi
> > > 
> > > [1] https://lore.kernel.org/all/IA1PR20MB4953CA5D46EA8913B130D502BB052@IA1PR20MB4953.namprd20.prod.outlook.com/
> > I make a mistake when reordering the url.
> > [1] should be https://lore.kernel.org/all/IA1PR20MB49537E8B2D1FAAA7D5B8BDA2BB052@IA1PR20MB4953.namprd20.prod.outlook.com/
> 
> 
> Indeed, I was using the "defconfig" config. Too used to having everything
> working with this configuration on RISC-V :-/
> 

I apologize for this mistake. I just forgot this after removing
default value in the Kconfig.

> Gotcha for the CONFIG_CLK_SOPHGO_CV1800 setting. However, I'm confused. Why
> is this setting available in linux-next, but neither in
> git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git ("master" and
> "for-next") nor in github.com/sophgo/linux.git ("master" and "for-next") ?

At now, we only maintain the dts related change, but not the driver 
code. The driver code is usually applied by the subsystem maintainer. 
This is why you only see the clk changes in the linux-next.

> 
> What's the tree used to push to linux-next?
> 

As you see, the driver code applied to the clk/for-next. That is the
tree used to push.

Michael Opdenacker April 15, 2024, 7:44 a.m. UTC | #8

Hi Inochi

On 4/14/24 at 11:41, Inochi Amaoto wrote:
>> Gotcha for the CONFIG_CLK_SOPHGO_CV1800 setting. However, I'm confused. Why
>> is this setting available in linux-next, but neither in
>> git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git ("master" and
>> "for-next") nor in github.com/sophgo/linux.git ("master" and "for-next") ?
> At now, we only maintain the dts related change, but not the driver
> code. The driver code is usually applied by the subsystem maintainer.
> This is why you only see the clk changes in the linux-next.
>
>> What's the tree used to push to linux-next?
>>
> As you see, the driver code applied to the clk/for-next. That is the
> tree used to push.

It makes perfect sense, thanks!

So, I tried to boot my Milk-V Duo S board with the latest linux-next 
kernel (with CONFIG_CLK_SOPHGO_CV1800=y). Here's what I'm getting:

[    1.933301] mmc0: SDHCI controller on 4310000.mmc [4310000.mmc] using ADMA 64-bit
[    1.947274] Legacy PMU implementation is available
[    1.954001] clk: Disabling unused clocks
[    1.959283] PM: genpd: Disabling unused power domains
[    1.964840] ALSA device list:
[    1.968165]   No soundcards found.
[    1.975652] dw-apb-uart 4140000.serial: forbid DMA for kernel console
[    2.133075] mmc0: Internal clock never stabilised.
[    2.138256] mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
[    2.145082] mmc0: sdhci: Sys addr:  0x00000000 | Version:  0x00000000
[    2.151906] mmc0: sdhci: Blk size:  0x00000000 | Blk cnt:  0x00000000
[    2.158725] mmc0: sdhci: Argument:  0x00000000 | Trn mode: 0x00000000
[    2.165543] mmc0: sdhci: Present:   0x00000000 | Host ctl: 0x00000000
[    2.172362] mmc0: sdhci: Power:     0x00000000 | Blk gap:  0x00000000
[    2.179220] mmc0: sdhci: Wake-up:   0x00000000 | Clock:    0x00000000
[    2.186056] mmc0: sdhci: Timeout:   0x00000000 | Int stat: 0x00000000
[    2.192878] mmc0: sdhci: Int enab:  0x00000000 | Sig enab: 0x00000000
[    2.199699] mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
[    2.206520] mmc0: sdhci: Caps:      0x00000000 | Caps_1:   0x00000000
[    2.213342] mmc0: sdhci: Cmd:       0x00000000 | Max curr: 0x00000000
[    2.220162] mmc0: sdhci: Resp[0]:   0x00000000 | Resp[1]:  0x00000000
[    2.226983] mmc0: sdhci: Resp[2]:   0x00000000 | Resp[3]:  0x00000000
[    2.233798] mmc0: sdhci: Host ctl2: 0x00000000
[    2.238558] mmc0: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x0000000000000000
[    2.246189] mmc0: sdhci: ============================================
[    2.256290] /dev/root: Can't open blockdev
[    2.261025] VFS: Cannot open root device "/dev/mmcblk0p2" or unknown-block(0,0): error -6

Here's my device tree (compiled with the sophgo for-next) branch:

/dts-v1/;

#include "cv1812h.dtsi"

/ {
         model = "Milk-V Duo S";
         compatible = "milkv,duos", "sophgo,cv1812h";

         aliases {
                 serial0 = &uart0;
         };

         chosen {
                 stdout-path = "serial0:115200n8";
         };

         memory@80000000 {
                 device_type = "memory";
                 reg = <0x80000000 0x20000000>;
         };
};

&osc {
         clock-frequency = <25000000>;
};

&sdhci0 {
         status = "okay";
         bus-width = <4>;
         no-mmc;
         no-sdio;
         disable-wp;
};

&uart0 {
         status = "okay";
};


What's frustrating is that I got the mmc working a few days back :-)
Hoping this helps...
Cheers
Michael.

[v9,0/6] riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs

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