| Message ID | 20240415-rzn1-gmac1-v3-5-ab12f2c4401d@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | net: stmmac: Add support for RZN1 GMAC devices | expand |
Hi Romain, On Mon, Apr 15, 2024 at 11:18 AM Romain Gantois <romain.gantois@bootlin.com> wrote: > From: Clément Léger <clement.leger@bootlin.com> > > The r9a06g032 SoC of the RZ/N1 family features two GMAC devices named > GMAC1/2, that are based on Synopsys cores. GMAC1 is connected to a > RGMII/RMII converter that is already described in this device tree. > > Signed-off-by: "Clément Léger" <clement.leger@bootlin.com> > [rgantois: commit log] > Signed-off-by: Romain Gantois <romain.gantois@bootlin.com> Thanks for your patch! > --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi > @@ -316,6 +316,25 @@ dma1: dma-controller@40105000 { > data-width = <8>; > }; > > + gmac1: ethernet@44000000 { > + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; > + reg = <0x44000000 0x2000>; > + interrupt-parent = <&gic>; The surrounding "soc" node already specifies the interrupt parent, so there is no need to repeat that. I could fix that while applying to renesas-devel for v6.10, but it looks like there will be a v4 for the rest of the series anyway? The rest LGTM, so with the above fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; > + clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; > + clock-names = "stmmaceth"; > + power-domains = <&sysctrl>; > + snps,multicast-filter-bins = <256>; > + snps,perfect-filter-entries = <128>; > + tx-fifo-depth = <2048>; > + rx-fifo-depth = <4096>; > + pcs-handle = <&mii_conv1>; > + status = "disabled"; > + }; > + > gmac2: ethernet@44002000 { > compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; > reg = <0x44002000 0x2000>; > Gr{oetje,eeting}s, Geert
Hi Geert, On Thu, 18 Apr 2024, Geert Uytterhoeven wrote: > > + gmac1: ethernet@44000000 { > > + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; > > + reg = <0x44000000 0x2000>; > > + interrupt-parent = <&gic>; > > The surrounding "soc" node already specifies the interrupt parent, > so there is no need to repeat that. I could fix that while applying > to renesas-devel for v6.10, but it looks like there will be a v4 for > the rest of the series anyway? Indeed there will be a v4 so I'll fix it. Thanks,
diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index fa63e1afc4ef4..cab7a641f95ba 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -316,6 +316,25 @@ dma1: dma-controller@40105000 { data-width = <8>; }; + gmac1: ethernet@44000000 { + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; + reg = <0x44000000 0x2000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; + clock-names = "stmmaceth"; + power-domains = <&sysctrl>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + pcs-handle = <&mii_conv1>; + status = "disabled"; + }; + gmac2: ethernet@44002000 { compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; reg = <0x44002000 0x2000>;