| Message ID | 20240416063927.99428-3-rathc@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/ppc: Move fixed-point insns to decodetree. | expand |
On 4/15/24 23:39, Chinmay Rath wrote: > The handler methods for divw[u] instructions internally use Rc(ctx->opcode), > for extraction of Rc field of instructions, which poses a problem if we move > the above said instructions to decodetree, as the ctx->opcode field is not > popluated in decodetree. Hence, making it decodetree compatible, so that the > mentioned insns can be safely move to decodetree specs. > > Signed-off-by: Chinmay Rath<rathc@linux.ibm.com> > --- > target/ppc/translate.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > +static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, > + TCGv arg1, TCGv arg2, bool sign, > + bool compute_ov, bool compute_rc0) Could drop the inline at the same time. Let the compiler decide. r~
Hi Richard, On 4/16/24 23:27, Richard Henderson wrote: > On 4/15/24 23:39, Chinmay Rath wrote: >> The handler methods for divw[u] instructions internally use >> Rc(ctx->opcode), >> for extraction of Rc field of instructions, which poses a problem if >> we move >> the above said instructions to decodetree, as the ctx->opcode field >> is not >> popluated in decodetree. Hence, making it decodetree compatible, so >> that the >> mentioned insns can be safely move to decodetree specs. >> >> Signed-off-by: Chinmay Rath<rathc@linux.ibm.com> >> --- >> target/ppc/translate.c | 9 +++++---- >> 1 file changed, 5 insertions(+), 4 deletions(-) > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Thank you. >> +static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, >> + TCGv arg1, TCGv arg2, bool sign, >> + bool compute_ov, bool compute_rc0) > > Could drop the inline at the same time. > Let the compiler decide. > I kept inline as is, as there are multiple gen_op_* routines with inline and if necessary we could consider removing inline for all of them together in a separate patch : grep inline target/ppc/translate.c | grep gen_op static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, static inline void gen_op_arith_compute_ca32(DisasContext *ctx, static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, static inline void gen_op_mfspr(DisasContext *ctx) Thanks, Chinmay > > r~
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c45547a770..be7d807e3c 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1738,8 +1738,9 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, } } -static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, - TCGv arg2, int sign, int compute_ov) +static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, + TCGv arg1, TCGv arg2, bool sign, + bool compute_ov, bool compute_rc0) { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); @@ -1773,7 +1774,7 @@ static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); } - if (unlikely(Rc(ctx->opcode) != 0)) { + if (unlikely(compute_rc0)) { gen_set_Rc0(ctx, ret); } } @@ -1783,7 +1784,7 @@ static void glue(gen_, name)(DisasContext *ctx) \ { \ gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ - sign, compute_ov); \ + sign, compute_ov, Rc(ctx->opcode)); \ } /* divwu divwu. divwuo divwuo. */ GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
The handler methods for divw[u] instructions internally use Rc(ctx->opcode), for extraction of Rc field of instructions, which poses a problem if we move the above said instructions to decodetree, as the ctx->opcode field is not popluated in decodetree. Hence, making it decodetree compatible, so that the mentioned insns can be safely move to decodetree specs. Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> --- target/ppc/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)