diff mbox series

[5.10.y-cip,17/53] clk: renesas: rzg2l: Add support for RZ/G3S PLL

Message ID 20240419081742.3496709-18-claudiu.beznea.uj@bp.renesas.com (mailing list archive)
State New
Headers show
Series Add initial support for the Renesas RZ/G3S SoC | expand

Commit Message

Claudiu Beznea April 19, 2024, 8:17 a.m. UTC 
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

commit 01eabef547e63d80086acd3f247d36c5f9f92456 upstream.

Add support for reading the frequency of PLL1/4/6 as available on
RZ/G3S.  The computation formula for the PLL frequency is as follows:

    Fout = (nir + nfr / 4096) * Fin / (mr * pr)

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-8-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/clk/renesas/rzg2l-cpg.c | 49 ++++++++++++++++++++++++++++++---
 drivers/clk/renesas/rzg2l-cpg.h |  3 ++
 2 files changed, 48 insertions(+), 4 deletions(-)

Comments

Pavel Machek April 21, 2024, 2:18 p.m. UTC | #1 
Hi!

> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -714,11 +719,43 @@ static const struct clk_ops rzg2l_cpg_pll_ops = {
> +static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
> +						   unsigned long parent_rate)
> +{
...
> +	val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
> +
> +	pr = 1 << FIELD_GET(RZG3S_DIV_P, val);
> +	/* Hardware interprets values higher than 8 as p = 16. */
> +	if (pr > 8)
> +		pr = 16;

What does "p" mean in the above comment. Should it say "pr"?

Best regards,
							Pavel
Claudiu Beznea April 22, 2024, 4:43 a.m. UTC | #2 
Hi, Pavel,

On 21.04.2024 17:18, Pavel Machek wrote:
> Hi!
> 
>> +++ b/drivers/clk/renesas/rzg2l-cpg.c
>> @@ -714,11 +719,43 @@ static const struct clk_ops rzg2l_cpg_pll_ops = {
>> +static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
>> +						   unsigned long parent_rate)
>> +{
> ...
>> +	val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
>> +
>> +	pr = 1 << FIELD_GET(RZG3S_DIV_P, val);
>> +	/* Hardware interprets values higher than 8 as p = 16. */
>> +	if (pr > 8)
>> +		pr = 16;
> 
> What does "p" mean in the above comment. Should it say "pr"?

Yes, it should be "pr". I'll update it in upstream kernel.

Thank you,
Claudiu Beznea

> 
> Best regards,
> 							Pavel
diff mbox series

Patch

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index b280a468c4a8..1a928828baac 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -48,6 +48,11 @@ 
 #define PDIV(val)		FIELD_GET(GENMASK(5, 0), val)
 #define SDIV(val)		FIELD_GET(GENMASK(2, 0), val)
 
+#define RZG3S_DIV_P		GENMASK(28, 26)
+#define RZG3S_DIV_M		GENMASK(25, 22)
+#define RZG3S_DIV_NI		GENMASK(21, 13)
+#define RZG3S_DIV_NF		GENMASK(12, 1)
+
 #define CLK_ON_R(reg)		(reg)
 #define CLK_MON_R(reg)		(0x180 + (reg))
 #define CLK_RST_R(reg)		(reg)
@@ -714,11 +719,43 @@  static const struct clk_ops rzg2l_cpg_pll_ops = {
 	.recalc_rate = rzg2l_cpg_pll_clk_recalc_rate,
 };
 
+static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
+						   unsigned long parent_rate)
+{
+	struct pll_clk *pll_clk = to_pll(hw);
+	struct rzg2l_cpg_priv *priv = pll_clk->priv;
+	u32 nir, nfr, mr, pr, val;
+	u64 rate;
+
+	if (pll_clk->type != CLK_TYPE_G3S_PLL)
+		return parent_rate;
+
+	val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
+
+	pr = 1 << FIELD_GET(RZG3S_DIV_P, val);
+	/* Hardware interprets values higher than 8 as p = 16. */
+	if (pr > 8)
+		pr = 16;
+
+	mr  = FIELD_GET(RZG3S_DIV_M, val) + 1;
+	nir = FIELD_GET(RZG3S_DIV_NI, val) + 1;
+	nfr = FIELD_GET(RZG3S_DIV_NF, val);
+
+	rate = mul_u64_u32_shr(parent_rate, 4096 * nir + nfr, 12);
+
+	return DIV_ROUND_CLOSEST_ULL(rate, (mr * pr));
+}
+
+static const struct clk_ops rzg3s_cpg_pll_ops = {
+	.recalc_rate = rzg3s_cpg_pll_clk_recalc_rate,
+};
+
 static struct clk * __init
 rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
 			   struct clk **clks,
 			   void __iomem *base,
-			   struct rzg2l_cpg_priv *priv)
+			   struct rzg2l_cpg_priv *priv,
+			   const struct clk_ops *ops)
 {
 	struct device *dev = priv->dev;
 	const struct clk *parent;
@@ -736,7 +773,7 @@  rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
 
 	parent_name = __clk_get_name(parent);
 	init.name = core->name;
-	init.ops = &rzg2l_cpg_pll_ops;
+	init.ops = ops;
 	init.flags = 0;
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
@@ -831,8 +868,12 @@  rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
 						core->mult, div);
 		break;
 	case CLK_TYPE_SAM_PLL:
-		clk = rzg2l_cpg_pll_clk_register(core, priv->clks,
-						 priv->base, priv);
+		clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,
+						 &rzg2l_cpg_pll_ops);
+		break;
+	case CLK_TYPE_G3S_PLL:
+		clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,
+						 &rzg3s_cpg_pll_ops);
 		break;
 	case CLK_TYPE_SIPLL5:
 		clk = rzg2l_cpg_sipll5_register(core, priv->clks, priv);
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 097fd8f61680..20da0c620b90 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -102,6 +102,7 @@  enum clk_types {
 	CLK_TYPE_IN,		/* External Clock Input */
 	CLK_TYPE_FF,		/* Fixed Factor Clock */
 	CLK_TYPE_SAM_PLL,
+	CLK_TYPE_G3S_PLL,
 
 	/* Clock with divider */
 	CLK_TYPE_DIV,
@@ -129,6 +130,8 @@  enum clk_types {
 	DEF_TYPE(_name, _id, _type, .parent = _parent)
 #define DEF_SAMPLL(_name, _id, _parent, _conf) \
 	DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
+#define DEF_G3S_PLL(_name, _id, _parent, _conf) \
+	DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf)
 #define DEF_INPUT(_name, _id) \
 	DEF_TYPE(_name, _id, CLK_TYPE_IN)
 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \