| Message ID | 20240424110047.21766-2-jhp@endlessos.org (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | PCI: vmd: Enable PCI PM's L1 substates of remapped PCIe Root Port and NVMe | expand |
On Wed, 2024-04-24 at 19:00 +0800, Jian-Hong Pan wrote: > Introduce aspm_get_l1ss_cap() which is extracted from aspm_l1ss_init() to > get the PCIe's L1SS capability. This does not change any behavior, but > aspm_get_l1ss_cap() can be reused later. > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=218394 > Signed-off-by: Jian-Hong Pan <jhp@endlessos.org> > --- > drivers/pci/pcie/aspm.c | 23 ++++++++++++++--------- > 1 file changed, 14 insertions(+), 9 deletions(-) > > diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c > index 91a8b35b1ae2..c55ac11faa73 100644 > --- a/drivers/pci/pcie/aspm.c > +++ b/drivers/pci/pcie/aspm.c > @@ -612,6 +612,18 @@ static void pcie_aspm_check_latency(struct pci_dev > *endpoint) > } > } > > +static u32 aspm_get_l1ss_cap(struct pci_dev *pdev) > +{ > + u32 l1ss_cap; > + > + pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CAP, &l1ss_cap); > + > + if (!(l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) > + l1ss_cap = 0; > + > + return l1ss_cap; > +} > + > /* Calculate L1.2 PM substate timing parameters */ > static void aspm_calc_l12_info(struct pcie_link_state *link, > u32 parent_l1ss_cap, u32 child_l1ss_cap) > @@ -722,15 +734,8 @@ static void aspm_l1ss_init(struct pcie_link_state *link) > return; > > /* Setup L1 substate */ > - pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, > - &parent_l1ss_cap); > - pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP, > - &child_l1ss_cap); > - > - if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) > - parent_l1ss_cap = 0; > - if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) > - child_l1ss_cap = 0; > + parent_l1ss_cap = aspm_get_l1ss_cap(parent); > + child_l1ss_cap = aspm_get_l1ss_cap(child); > > /* > * If we don't have LTR for the entire path from the Root Complex Reviewed-by: David E. Box <david.e.box@linux.intel.com>
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 91a8b35b1ae2..c55ac11faa73 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -612,6 +612,18 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) } } +static u32 aspm_get_l1ss_cap(struct pci_dev *pdev) +{ + u32 l1ss_cap; + + pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CAP, &l1ss_cap); + + if (!(l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) + l1ss_cap = 0; + + return l1ss_cap; +} + /* Calculate L1.2 PM substate timing parameters */ static void aspm_calc_l12_info(struct pcie_link_state *link, u32 parent_l1ss_cap, u32 child_l1ss_cap) @@ -722,15 +734,8 @@ static void aspm_l1ss_init(struct pcie_link_state *link) return; /* Setup L1 substate */ - pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, - &parent_l1ss_cap); - pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP, - &child_l1ss_cap); - - if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) - parent_l1ss_cap = 0; - if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) - child_l1ss_cap = 0; + parent_l1ss_cap = aspm_get_l1ss_cap(parent); + child_l1ss_cap = aspm_get_l1ss_cap(child); /* * If we don't have LTR for the entire path from the Root Complex
Introduce aspm_get_l1ss_cap() which is extracted from aspm_l1ss_init() to get the PCIe's L1SS capability. This does not change any behavior, but aspm_get_l1ss_cap() can be reused later. Link: https://bugzilla.kernel.org/show_bug.cgi?id=218394 Signed-off-by: Jian-Hong Pan <jhp@endlessos.org> --- drivers/pci/pcie/aspm.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-)