| Message ID | 20240402-pci2_upstream-v3-2-803414bdb430@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: imx6: Fix\rename\clean up and add lut information for imx95 | expand |
On Tue, Apr 02, 2024 at 10:33:38AM -0400, Frank Li wrote: > From: Richard Zhu <hongxing.zhu@nxp.com> > > Fix i.MX8MP PCIe EP can't trigger MSI issue. > There is one 64Kbytes minimal requirement on i.MX8M PCIe outbound > region configuration. > > EP uses Bar0 to set the outboud region to configure the MSI setting. I don't understand this statement. How EP can use BAR0 for MSI? MSIs are triggered using outbound window memory while BARs are mapped as inbound. - Mani > Set the page_size to "epc_features->align" to meet the requirement, > let the MSI can be triggered successfully. > > Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code") > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Acked-by: Jason Liu <jason.hui.liu@nxp.com> > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index e43eda6b33ca7..6c4d25b92225e 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > > + ep->page_size = imx6_pcie->drvdata->epc_features->align; > + > ret = dw_pcie_ep_init(ep); > if (ret) { > dev_err(dev, "failed to initialize endpoint\n"); > > -- > 2.34.1 >
On Sat, Apr 27, 2024 at 02:53:03PM +0530, Manivannan Sadhasivam wrote: > On Tue, Apr 02, 2024 at 10:33:38AM -0400, Frank Li wrote: > > From: Richard Zhu <hongxing.zhu@nxp.com> > > > > Fix i.MX8MP PCIe EP can't trigger MSI issue. > > There is one 64Kbytes minimal requirement on i.MX8M PCIe outbound > > region configuration. > > > > EP uses Bar0 to set the outboud region to configure the MSI setting. > > I don't understand this statement. How EP can use BAR0 for MSI? MSIs are > triggered using outbound window memory while BARs are mapped as inbound. > > - Mani Let's rewrite commit message. PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI i.MX8MP PCIe EP requires 64KB alignment. MSI triggering may fail if the outbound MSI memory region (ep->msi_mem) is not aligned to 64KB. In dw_pcie_ep_init(): ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, epc->mem->window.page_size); Set ep->page_size to match drvdata::epc_features::align since different SOCs have different alignment requirements. Frank > > > Set the page_size to "epc_features->align" to meet the requirement, > > let the MSI can be triggered successfully. > > > > Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code") > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > Acked-by: Jason Liu <jason.hui.liu@nxp.com> > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > drivers/pci/controller/dwc/pci-imx6.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > > index e43eda6b33ca7..6c4d25b92225e 100644 > > --- a/drivers/pci/controller/dwc/pci-imx6.c > > +++ b/drivers/pci/controller/dwc/pci-imx6.c > > @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > > if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > > > > + ep->page_size = imx6_pcie->drvdata->epc_features->align; > > + > > ret = dw_pcie_ep_init(ep); > > if (ret) { > > dev_err(dev, "failed to initialize endpoint\n"); > > > > -- > > 2.34.1 > > > > -- > மணிவண்ணன் சதாசிவம்
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index e43eda6b33ca7..6c4d25b92225e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1118,6 +1118,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + ep->page_size = imx6_pcie->drvdata->epc_features->align; + ret = dw_pcie_ep_init(ep); if (ret) { dev_err(dev, "failed to initialize endpoint\n");