| Message ID | 20240428091133.592333-1-Xiaojian.Du@amd.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | [1/2] x86/cpufeatures: Add AMD FAST CPPC feature flag | expand |
+ lkml On Sun, Apr 28, 2024 at 05:11:32PM +0800, Xiaojian Du wrote: > From: Perry Yuan <perry.yuan@amd.com> > > Some AMD Zen 4 processors support a new feature FAST CPPC which > allows for a faster CPPC loop due to internal architectual > enhancements. The goal of this faster loop is higher performance > at the same power consumption. > > Reference: > Page 99 of PPR for AMD Family 19h Model 61h rev.B1 > https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/56713-B1_3_05.zip This should say "See the PPR for AMD Family 19h Model 61h rev.B1, docID 56713" so that people can actually find it. The URLs are flaky and change regularly so can't use them. > Signed-off-by: Perry Yuan <perry.yuan@amd.com> > Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/scattered.c | 1 + > 2 files changed, 2 insertions(+) Always use ./scripts/get_maintainer.pl when sending a patch to know who to Cc. Also, have a look at those to get an idea how the process works: https://kernel.org/doc/html/latest/process/development-process.html https://kernel.org/doc/html/latest/process/submitting-patches.html > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 3c7434329661..6c128d463a14 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -470,6 +470,7 @@ > #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */ > #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */ > #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */ > +#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* "" AMD Fast CPPC */ > > /* > * BUG word(s) > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c > index af5aa2c754c2..9c273c231f56 100644 > --- a/arch/x86/kernel/cpu/scattered.c > +++ b/arch/x86/kernel/cpu/scattered.c > @@ -51,6 +51,7 @@ static const struct cpuid_bit cpuid_bits[] = { > { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, > { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, > { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, > + { X86_FEATURE_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, > { 0, 0, 0, 0, 0 } > }; > With the above addressed: Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
[AMD Official Use Only - General] Thanks a lot for review, I will modify before submitting. Xiaojian -----Original Message----- From: Borislav Petkov <bp@alien8.de> Sent: Sunday, April 28, 2024 5:54 PM To: Du, Xiaojian <Xiaojian.Du@amd.com> Cc: linux-pm@vger.kernel.org; Shenoy, Gautham Ranjal <gautham.shenoy@amd.com>; Limonciello, Mario <Mario.Limonciello@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Yuan, Perry <Perry.Yuan@amd.com>; lkml <linux-kernel@vger.kernel.org> Subject: Re: [PATCH 1/2] x86/cpufeatures: Add AMD FAST CPPC feature flag + lkml On Sun, Apr 28, 2024 at 05:11:32PM +0800, Xiaojian Du wrote: > From: Perry Yuan <perry.yuan@amd.com> > > Some AMD Zen 4 processors support a new feature FAST CPPC which allows > for a faster CPPC loop due to internal architectual enhancements. The > goal of this faster loop is higher performance at the same power > consumption. > > Reference: > Page 99 of PPR for AMD Family 19h Model 61h rev.B1 > https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/p > rogrammer-references/56713-B1_3_05.zip This should say "See the PPR for AMD Family 19h Model 61h rev.B1, docID 56713" so that people can actually find it. The URLs are flaky and change regularly so can't use them. > Signed-off-by: Perry Yuan <perry.yuan@amd.com> > Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/scattered.c | 1 + > 2 files changed, 2 insertions(+) Always use ./scripts/get_maintainer.pl when sending a patch to know who to Cc. Also, have a look at those to get an idea how the process works: https://kernel.org/doc/html/latest/process/development-process.html https://kernel.org/doc/html/latest/process/submitting-patches.html > > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > index 3c7434329661..6c128d463a14 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -470,6 +470,7 @@ > #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */ > #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */ > #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear > branch history at vmexit using SW loop */ > +#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* "" AMD Fast CPPC */ > > /* > * BUG word(s) > diff --git a/arch/x86/kernel/cpu/scattered.c > b/arch/x86/kernel/cpu/scattered.c index af5aa2c754c2..9c273c231f56 > 100644 > --- a/arch/x86/kernel/cpu/scattered.c > +++ b/arch/x86/kernel/cpu/scattered.c > @@ -51,6 +51,7 @@ static const struct cpuid_bit cpuid_bits[] = { > { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, > { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, > { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, > + { X86_FEATURE_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, > { 0, 0, 0, 0, 0 } > }; > With the above addressed: Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette
On Sun, Apr 28, 2024 at 10:59:50AM +0000, Du, Xiaojian wrote:
> Thanks a lot for review, I will modify before submitting.
Thanks.
Also, please do not top-post on a public ML but put your reply
underneath, like I just did.
That's also explained in those docs I pointed you to.
Thx.
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 3c7434329661..6c128d463a14 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -470,6 +470,7 @@ #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */ +#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* "" AMD Fast CPPC */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index af5aa2c754c2..9c273c231f56 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -51,6 +51,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, + { X86_FEATURE_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, { 0, 0, 0, 0, 0 } };