diff mbox series

[v2] drm/i915: pass dev_priv explicitly to PSR2_SU_STATUS

Message ID 20240502103925.1829104-1-jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show
Series [v2] drm/i915: pass dev_priv explicitly to PSR2_SU_STATUS | expand

Commit Message

Jani Nikula May 2, 2024, 10:39 a.m. UTC
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR2_SU_STATUS register macro.

v2: Expand from _PSR2_SU_STATUS to PSR2_SU_STATUS (Rodrigo)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 3 ++-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

Comments

Rodrigo Vivi May 2, 2024, 12:55 p.m. UTC | #1
On Thu, May 02, 2024 at 01:39:25PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PSR2_SU_STATUS register macro.
> 
> v2: Expand from _PSR2_SU_STATUS to PSR2_SU_STATUS (Rodrigo)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 3 ++-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 36c08cd3a624..0412a2e1d638 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3569,7 +3569,8 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
>  		 * frame boundary between register reads
>  		 */
>  		for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
> -			val = intel_de_read(dev_priv, PSR2_SU_STATUS(cpu_transcoder, frame));
> +			val = intel_de_read(dev_priv,
> +					    PSR2_SU_STATUS(dev_priv, cpu_transcoder, frame));
>  			su_frames_val[frame / 3] = val;
>  		}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index e6c62512512f..5504593aa9d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -221,8 +221,8 @@
>  
>  #define _PSR2_SU_STATUS_A		0x60914
>  #define _PSR2_SU_STATUS_EDP		0x6f914
> -#define _PSR2_SU_STATUS(tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
> -#define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(tran, (frame) / 3))
> +#define _PSR2_SU_STATUS(dev_priv, tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
> +#define PSR2_SU_STATUS(dev_priv, tran, frame)	(_PSR2_SU_STATUS(dev_priv, tran, (frame) / 3))
>  #define PSR2_SU_STATUS_SHIFT(frame)	(((frame) % 3) * 10)
>  #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
>  #define PSR2_SU_STATUS_FRAMES		8
> -- 
> 2.39.2
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 36c08cd3a624..0412a2e1d638 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3569,7 +3569,8 @@  static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 		 * frame boundary between register reads
 		 */
 		for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
-			val = intel_de_read(dev_priv, PSR2_SU_STATUS(cpu_transcoder, frame));
+			val = intel_de_read(dev_priv,
+					    PSR2_SU_STATUS(dev_priv, cpu_transcoder, frame));
 			su_frames_val[frame / 3] = val;
 		}
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index e6c62512512f..5504593aa9d0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -221,8 +221,8 @@ 
 
 #define _PSR2_SU_STATUS_A		0x60914
 #define _PSR2_SU_STATUS_EDP		0x6f914
-#define _PSR2_SU_STATUS(tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
-#define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(tran, (frame) / 3))
+#define _PSR2_SU_STATUS(dev_priv, tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
+#define PSR2_SU_STATUS(dev_priv, tran, frame)	(_PSR2_SU_STATUS(dev_priv, tran, (frame) / 3))
 #define PSR2_SU_STATUS_SHIFT(frame)	(((frame) % 3) * 10)
 #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
 #define PSR2_SU_STATUS_FRAMES		8