diff mbox series

[v7,09/18] drm/mediatek: Support constant blending in OVL

Message ID 20240502103848.5845-10-shawn.sung@mediatek.com (mailing list archive)
State New, archived
Headers show
Series Support IGT in display driver | expand

Commit Message

Shawn Sung (宋孝謙) May 2, 2024, 10:38 a.m. UTC 
From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Support constant alpha blending in OVL.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

Comments

CK Hu (胡俊光) May 3, 2024, 5:29 a.m. UTC | #1 
Hi, Shawn:

On Thu, 2024-05-02 at 18:38 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> 
> Support constant alpha blending in OVL.

What is constant alpha? I search in wikipedia but find nothing about
constant alpha. This is not a common term, so explain it.

Regards,
CK

> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 738244a6164e8..e41fd83e36e79 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -38,6 +38,7 @@
>  #define DISP_REG_OVL_PITCH_MSB(n)		(0x0040 + 0x20 * (n))
>  #define OVL_PITCH_MSB_2ND_SUBBUF			BIT(16)
>  #define DISP_REG_OVL_PITCH(n)			(0x0044 + 0x20
> * (n))
> +#define OVL_CONST_BLEND					BIT(28)
>  #define DISP_REG_OVL_RDMA_CTRL(n)		(0x00c0 + 0x20 * (n))
>  #define DISP_REG_OVL_RDMA_GMC(n)		(0x00c8 + 0x20 * (n))
>  #define DISP_REG_OVL_ADDR_MT2701		0x0040
> @@ -428,6 +429,7 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
>  	unsigned int fmt = pending->format;
>  	unsigned int offset = (pending->y << 16) | pending->x;
>  	unsigned int src_size = (pending->height << 16) | pending-
> >width;
> +	unsigned int ignore_pixel_alpha = 0;
>  	unsigned int con;
>  	bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
>  	union overlay_pitch {
> @@ -449,6 +451,9 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
>  	if (state->base.fb && state->base.fb->format->has_alpha)
>  		con |= OVL_CON_AEN | OVL_CON_ALPHA;
>  
> +	if (state->base.fb && !state->base.fb->format->has_alpha)
> +		ignore_pixel_alpha = OVL_CONST_BLEND;
> +
>  	if (pending->rotation & DRM_MODE_REFLECT_Y) {
>  		con |= OVL_CON_VIRT_FLIP;
>  		addr += (pending->height - 1) * pending->pitch;
> @@ -464,8 +469,8 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
>  
>  	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
>  			      DISP_REG_OVL_CON(idx));
> -	mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb,
> &ovl->cmdq_reg, ovl->regs,
> -			      DISP_REG_OVL_PITCH(idx));
> +	mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb |
> ignore_pixel_alpha,
> +			      &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_PITCH(idx));
>  	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl-
> >regs,
>  			      DISP_REG_OVL_SRC_SIZE(idx));
>  	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl-
> >regs,
CK Hu (胡俊光) May 3, 2024, 5:52 a.m. UTC | #2 
Hi, Shawn:

On Thu, 2024-05-02 at 18:38 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> 
> Support constant alpha blending in OVL.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 738244a6164e8..e41fd83e36e79 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -38,6 +38,7 @@
>  #define DISP_REG_OVL_PITCH_MSB(n)		(0x0040 + 0x20 * (n))
>  #define OVL_PITCH_MSB_2ND_SUBBUF			BIT(16)
>  #define DISP_REG_OVL_PITCH(n)			(0x0044 + 0x20
> * (n))
> +#define OVL_CONST_BLEND					BIT(28)
>  #define DISP_REG_OVL_RDMA_CTRL(n)		(0x00c0 + 0x20 * (n))
>  #define DISP_REG_OVL_RDMA_GMC(n)		(0x00c8 + 0x20 * (n))
>  #define DISP_REG_OVL_ADDR_MT2701		0x0040
> @@ -428,6 +429,7 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
>  	unsigned int fmt = pending->format;
>  	unsigned int offset = (pending->y << 16) | pending->x;
>  	unsigned int src_size = (pending->height << 16) | pending-
> >width;
> +	unsigned int ignore_pixel_alpha = 0;
>  	unsigned int con;
>  	bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
>  	union overlay_pitch {
> @@ -449,6 +451,9 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
>  	if (state->base.fb && state->base.fb->format->has_alpha)
>  		con |= OVL_CON_AEN | OVL_CON_ALPHA;
>  
> +	if (state->base.fb && !state->base.fb->format->has_alpha)
> +		ignore_pixel_alpha = OVL_CONST_BLEND;
> +
>  	if (pending->rotation & DRM_MODE_REFLECT_Y) {
>  		con |= OVL_CON_VIRT_FLIP;
>  		addr += (pending->height - 1) * pending->pitch;
> @@ -464,8 +469,8 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
>  
>  	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
>  			      DISP_REG_OVL_CON(idx));
> -	mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb,
> &ovl->cmdq_reg, ovl->regs,
> -			      DISP_REG_OVL_PITCH(idx));
> +	mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb |
> ignore_pixel_alpha,
> +			      &ovl->cmdq_reg, ovl->regs, 

In original code, RGB888 or other pixel format without alpha works
correctly. Why need to set this? If this is a bug fix, add Fixes tag.

Regards,
CK

> DISP_REG_OVL_PITCH(idx));
>  	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl-
> >regs,
>  			      DISP_REG_OVL_SRC_SIZE(idx));
>  	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl-
> >regs,
diff mbox series

Patch

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 738244a6164e8..e41fd83e36e79 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -38,6 +38,7 @@ 
 #define DISP_REG_OVL_PITCH_MSB(n)		(0x0040 + 0x20 * (n))
 #define OVL_PITCH_MSB_2ND_SUBBUF			BIT(16)
 #define DISP_REG_OVL_PITCH(n)			(0x0044 + 0x20 * (n))
+#define OVL_CONST_BLEND					BIT(28)
 #define DISP_REG_OVL_RDMA_CTRL(n)		(0x00c0 + 0x20 * (n))
 #define DISP_REG_OVL_RDMA_GMC(n)		(0x00c8 + 0x20 * (n))
 #define DISP_REG_OVL_ADDR_MT2701		0x0040
@@ -428,6 +429,7 @@  void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 	unsigned int fmt = pending->format;
 	unsigned int offset = (pending->y << 16) | pending->x;
 	unsigned int src_size = (pending->height << 16) | pending->width;
+	unsigned int ignore_pixel_alpha = 0;
 	unsigned int con;
 	bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
 	union overlay_pitch {
@@ -449,6 +451,9 @@  void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 	if (state->base.fb && state->base.fb->format->has_alpha)
 		con |= OVL_CON_AEN | OVL_CON_ALPHA;
 
+	if (state->base.fb && !state->base.fb->format->has_alpha)
+		ignore_pixel_alpha = OVL_CONST_BLEND;
+
 	if (pending->rotation & DRM_MODE_REFLECT_Y) {
 		con |= OVL_CON_VIRT_FLIP;
 		addr += (pending->height - 1) * pending->pitch;
@@ -464,8 +469,8 @@  void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 
 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
 			      DISP_REG_OVL_CON(idx));
-	mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs,
-			      DISP_REG_OVL_PITCH(idx));
+	mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pixel_alpha,
+			      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));
 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
 			      DISP_REG_OVL_SRC_SIZE(idx));
 	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,