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[v3,1/2] dt-bindings: phy: Add Sophgo CV1800 USB phy

Message ID IA1PR20MB4953612130BFC78A8E92F6C5BB1D2@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive)
State Handled Elsewhere
Headers show
Series riscv: sophgo: add USB phy support for CV18XX series | expand

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Commit Message

Inochi Amaoto May 5, 2024, 1:52 a.m. UTC 
The USB phy of Sophgo CV18XX series SoC needs to sense a pin called
"VBUS_DET" to get the right operation mode. If this pin is not
connected, it only supports setting the mode manually.

Add USB phy bindings for Sophgo CV18XX/SG200X series SoC.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 .../bindings/phy/sophgo,cv1800-usb-phy.yaml   | 71 +++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml

--
2.45.0

Comments

Krzysztof Kozlowski May 6, 2024, 6:51 a.m. UTC | #1 
On 05/05/2024 03:52, Inochi Amaoto wrote:
> The USB phy of Sophgo CV18XX series SoC needs to sense a pin called
> "VBUS_DET" to get the right operation mode. If this pin is not
> connected, it only supports setting the mode manually.
> 
> Add USB phy bindings for Sophgo CV18XX/SG200X series SoC.

...

> +
> +  clock-names:
> +    items:
> +      - const: phy
> +      - const: app
> +      - const: stb
> +      - const: lpm
> +
> +  vbus_det-gpios:

No underscores.

> +    description: GPIO to the USB OTG VBUS detect pin. This should not be
> +      defined if vbus_det pin and switch pin are connected, which may
> +      break the VBUS detection.

Why is this property of the PHY? VBUS pin goes to the connector, doesn't
it? It looks like you combined two or three (!!!) bindings into one.

> +    maxItems: 1
> +
> +  sophgo,switch-gpios:
> +    description: GPIO array for the phy to control connected switch. For

Switch? This is a binding of the phy, not switch...

> +      host mode, the driver will set these GPIOs to low one by one. For

Yeah, you mention driver which further confirms this is a property for
driver, not hardware.

Describe your hardware, not driver behavior.


> +      device mode, the driver will set these GPIOs to high in reverse
> +      order. For a reference design, see item description.
> +    minItems: 1
> +    items:
> +      - description: USB switch operation mode
> +      - description: USB switch host power control
> +
> +required:
> +  - compatible
> +  - "#phy-cells"
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    phy@48 {
> +      compatible = "sophgo,cv1800-usb-phy";
> +      reg = <0x48 0x4>;
> +      #phy-cells = <0>;
> +      clocks = <&clk 92>, <&clk 93>,
> +               <&clk 94>, <&clk 95>;
> +      clock-names = "phy", "app", "stb", "lpm";

Make the example complete.



Best regards,
Krzysztof
Inochi Amaoto May 6, 2024, 12:17 p.m. UTC | #2 
On Mon, May 06, 2024 at 08:51:59AM GMT, Krzysztof Kozlowski wrote:
> On 05/05/2024 03:52, Inochi Amaoto wrote:
> > The USB phy of Sophgo CV18XX series SoC needs to sense a pin called
> > "VBUS_DET" to get the right operation mode. If this pin is not
> > connected, it only supports setting the mode manually.
> > 
> > Add USB phy bindings for Sophgo CV18XX/SG200X series SoC.
> 
> ...
> 
> > +
> > +  clock-names:
> > +    items:
> > +      - const: phy
> > +      - const: app
> > +      - const: stb
> > +      - const: lpm
> > +
> > +  vbus_det-gpios:
> 
> No underscores.
> 

Thanks.

> > +    description: GPIO to the USB OTG VBUS detect pin. This should not be
> > +      defined if vbus_det pin and switch pin are connected, which may
> > +      break the VBUS detection.
> 
> Why is this property of the PHY? VBUS pin goes to the connector, doesn't
> it? It looks like you combined two or three (!!!) bindings into one.
> 

Yes, but I am not sure which is the best to write this bindings.
The topology of USB likes this:

controller -- phy -- switch --> (host) port/hub
                            --> (device) port

The vbus-detect connect to the device port, but it will change the mode for
both phy and switch. And the switch is just a switching circuit.
I am pretty confused on how to split this binding. I think it may like the 
following:

phy {
	switch {
		/* This is the switch in the follows */
		connector1 {
			/* host port */
		};
		connector2 {
			/* device port*/
			/* the vbus pin is here */
		};
	};
};

Could you share some suggestion on this?

> > +    maxItems: 1
> > +
> > +  sophgo,switch-gpios:
> > +    description: GPIO array for the phy to control connected switch. For
> 
> Switch? This is a binding of the phy, not switch...
> 

You are right, I think this switch may be more like a pattern device.

> > +      host mode, the driver will set these GPIOs to low one by one. For
> 
> Yeah, you mention driver which further confirms this is a property for
> driver, not hardware.
> 
> Describe your hardware, not driver behavior.

OK, I will remove this.

> 
> 
> > +      device mode, the driver will set these GPIOs to high in reverse
> > +      order. For a reference design, see item description.
> > +    minItems: 1
> > +    items:
> > +      - description: USB switch operation mode
> > +      - description: USB switch host power control
> > +
> > +required:
> > +  - compatible
> > +  - "#phy-cells"
> > +  - clocks
> > +  - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    phy@48 {
> > +      compatible = "sophgo,cv1800-usb-phy";
> > +      reg = <0x48 0x4>;
> > +      #phy-cells = <0>;
> > +      clocks = <&clk 92>, <&clk 93>,
> > +               <&clk 94>, <&clk 95>;
> > +      clock-names = "phy", "app", "stb", "lpm";
> 
> Make the example complete.
> 
> 
> 
> Best regards,
> Krzysztof
>
Rob Herring (Arm) May 7, 2024, 7:08 p.m. UTC | #3 
On Mon, May 06, 2024 at 08:17:30PM +0800, Inochi Amaoto wrote:
> On Mon, May 06, 2024 at 08:51:59AM GMT, Krzysztof Kozlowski wrote:
> > On 05/05/2024 03:52, Inochi Amaoto wrote:
> > > The USB phy of Sophgo CV18XX series SoC needs to sense a pin called
> > > "VBUS_DET" to get the right operation mode. If this pin is not
> > > connected, it only supports setting the mode manually.
> > > 
> > > Add USB phy bindings for Sophgo CV18XX/SG200X series SoC.
> > 
> > ...
> > 
> > > +
> > > +  clock-names:
> > > +    items:
> > > +      - const: phy
> > > +      - const: app
> > > +      - const: stb
> > > +      - const: lpm
> > > +
> > > +  vbus_det-gpios:
> > 
> > No underscores.
> > 
> 
> Thanks.
> 
> > > +    description: GPIO to the USB OTG VBUS detect pin. This should not be
> > > +      defined if vbus_det pin and switch pin are connected, which may
> > > +      break the VBUS detection.
> > 
> > Why is this property of the PHY? VBUS pin goes to the connector, doesn't
> > it? It looks like you combined two or three (!!!) bindings into one.
> > 
> 
> Yes, but I am not sure which is the best to write this bindings.
> The topology of USB likes this:
> 
> controller -- phy -- switch --> (host) port/hub
>                             --> (device) port
> 
> The vbus-detect connect to the device port, but it will change the mode for
> both phy and switch. And the switch is just a switching circuit.
> I am pretty confused on how to split this binding. I think it may like the 
> following:
> 
> phy {
> 	switch {
> 		/* This is the switch in the follows */
> 		connector1 {
> 			/* host port */
> 		};
> 		connector2 {
> 			/* device port*/
> 			/* the vbus pin is here */
> 		};
> 	};
> };
> 
> Could you share some suggestion on this?

Something like the above assuming 2 physical connectors, but probably 
should be a child of the USB controller or on its own. PHYs usually 
aren't put into a parent/child hierarchy, but are out of band.

Is this switch implemented on the board level? If so, you should create 
something that would work on any platform with a GPIO controlled USB 
switch like this. 

Rob
Inochi Amaoto May 10, 2024, 11:19 a.m. UTC | #4 
On Tue, May 07, 2024 at 02:08:29PM GMT, Rob Herring wrote:
> On Mon, May 06, 2024 at 08:17:30PM +0800, Inochi Amaoto wrote:
> > On Mon, May 06, 2024 at 08:51:59AM GMT, Krzysztof Kozlowski wrote:
> > > On 05/05/2024 03:52, Inochi Amaoto wrote:
> > > > The USB phy of Sophgo CV18XX series SoC needs to sense a pin called
> > > > "VBUS_DET" to get the right operation mode. If this pin is not
> > > > connected, it only supports setting the mode manually.
> > > > 
> > > > Add USB phy bindings for Sophgo CV18XX/SG200X series SoC.
> > > 
> > > ...
> > > 
> > > > +
> > > > +  clock-names:
> > > > +    items:
> > > > +      - const: phy
> > > > +      - const: app
> > > > +      - const: stb
> > > > +      - const: lpm
> > > > +
> > > > +  vbus_det-gpios:
> > > 
> > > No underscores.
> > > 
> > 
> > Thanks.
> > 
> > > > +    description: GPIO to the USB OTG VBUS detect pin. This should not be
> > > > +      defined if vbus_det pin and switch pin are connected, which may
> > > > +      break the VBUS detection.
> > > 
> > > Why is this property of the PHY? VBUS pin goes to the connector, doesn't
> > > it? It looks like you combined two or three (!!!) bindings into one.
> > > 
> > 
> > Yes, but I am not sure which is the best to write this bindings.
> > The topology of USB likes this:
> > 
> > controller -- phy -- switch --> (host) port/hub
> >                             --> (device) port
> > 
> > The vbus-detect connect to the device port, but it will change the mode for
> > both phy and switch. And the switch is just a switching circuit.
> > I am pretty confused on how to split this binding. I think it may like the 
> > following:
> > 
> > phy {
> > 	switch {
> > 		/* This is the switch in the follows */
> > 		connector1 {
> > 			/* host port */
> > 		};
> > 		connector2 {
> > 			/* device port*/
> > 			/* the vbus pin is here */
> > 		};
> > 	};
> > };
> > 
> > Could you share some suggestion on this?
> 
> Something like the above assuming 2 physical connectors, but probably 
> should be a child of the USB controller or on its own. PHYs usually 
> aren't put into a parent/child hierarchy, but are out of band.
> 

Yes, your are right. I should add port definition under the controller.

> Is this switch implemented on the board level? If so, you should create 
> something that would work on any platform with a GPIO controlled USB 
> switch like this. 
> 
> Rob

Yes, the switch is FSUSB30UMX. If I understand you correctly, I need to
add a driver to control this switch, right?


Regards,
Inochi
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml b/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml
new file mode 100644
index 000000000000..ae17a8f91b0e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml
@@ -0,0 +1,71 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/sophgo,cv1800-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CV18XX/SG200X USB 2.0 PHY
+
+maintainers:
+  - Inochi Amaoto <inochiama@outlook.com>
+
+properties:
+  compatible:
+    const: sophgo,cv1800-usb-phy
+
+  reg:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+  clocks:
+    items:
+      - description: PHY clock
+      - description: PHY app clock
+      - description: PHY stb clock
+      - description: PHY lpm clock
+
+  clock-names:
+    items:
+      - const: phy
+      - const: app
+      - const: stb
+      - const: lpm
+
+  vbus_det-gpios:
+    description: GPIO to the USB OTG VBUS detect pin. This should not be
+      defined if vbus_det pin and switch pin are connected, which may
+      break the VBUS detection.
+    maxItems: 1
+
+  sophgo,switch-gpios:
+    description: GPIO array for the phy to control connected switch. For
+      host mode, the driver will set these GPIOs to low one by one. For
+      device mode, the driver will set these GPIOs to high in reverse
+      order. For a reference design, see item description.
+    minItems: 1
+    items:
+      - description: USB switch operation mode
+      - description: USB switch host power control
+
+required:
+  - compatible
+  - "#phy-cells"
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    phy@48 {
+      compatible = "sophgo,cv1800-usb-phy";
+      reg = <0x48 0x4>;
+      #phy-cells = <0>;
+      clocks = <&clk 92>, <&clk 93>,
+               <&clk 94>, <&clk 95>;
+      clock-names = "phy", "app", "stb", "lpm";
+    };
+
+...