| Message ID | 20240426073638.45775-1-angus.chen@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mtl: Update workaround 14018778641 | expand |
Hi Angus, ... > @@ -1586,6 +1586,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > */ > wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); > > + wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); Can you please add the reference of the workaround in a comment here? Thanks, Andi > +
The original workaround was from https://patchwork.freedesktop.org/patch/533574/ Then, we don't apply WA to VDBOX, VEBOX and RENDER engine with the following patch https://patchwork.freedesktop.org/patch/543117/?series=119517&rev=1 But now we need this WA to cover VDBOX. On 4/29/2024 5:53 PM, Andi Shyti wrote: > Hi Angus, > > ... > >> @@ -1586,6 +1586,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) >> */ >> wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); >> >> + wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); > Can you please add the reference of the workaround in a comment > here? > > Thanks, > Andi > >> +
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Chen, > Angus > Sent: Tuesday, April 30, 2024 4:50 PM > To: Andi Shyti <andi.shyti@linux.intel.com> > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/i915/mtl: Update workaround 14018778641 > > The original workaround was from > https://patchwork.freedesktop.org/patch/533574/ > Then, we don't apply WA to VDBOX, VEBOX and RENDER engine with the > following patch > https://patchwork.freedesktop.org/patch/543117/?series=119517&rev=1 > But now we need this WA to cover VDBOX. > > On 4/29/2024 5:53 PM, Andi Shyti wrote: > > Hi Angus, > > > > ... > > > >> @@ -1586,6 +1586,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, > struct i915_wa_list *wal) > >> */ > >> wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); > >> > >> + wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); > > Can you please add the reference of the workaround in a comment here? As far as I know media team confirmed that there is no perf impact and this WA can be removed. As Andi said, reference would be help here. Thanks, Tejas > > > > Thanks, > > Andi > > > >> +
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index d1ab560fcdfc..bf14749f5792 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1586,6 +1586,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) */ wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); + wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); + /* Wa_22016670082 */ wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
The WA should be extended to cover VDBOX engine. We found that 28-channels 1080p VP9 encoding may hit this issue. Signed-off-by: Chen, Angus <angus.chen@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 ++ 1 file changed, 2 insertions(+)