| Message ID | 20240503063413.1008135-12-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Panel replay selective update support | expand |
> -----Original Message----- > From: Hogander, Jouni <jouni.hogander@intel.com> > Sent: Friday, May 3, 2024 12:04 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh <animesh.manna@intel.com>; Hogander, Jouni > <jouni.hogander@intel.com> > Subject: [PATCH v9 11/12] drm/i915/psr: Split intel_psr2_config_valid for > panel replay > > Part of intel_psr2_config_valid is valid for panel replay. rename it as > intel_sel_update_config_valid. Split psr2 specific part and name it as > intel_psr2_config_valid. > > v3: > - move early transport check to psr2 specific check > - check intel_psr2_config_valid only for non-Panel Replay case > v2: > - use psr2_global_enabled for panel replay as well > - goto unsupported instead of return when global enabled check fails > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> LGTM. Reviewed-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 76 ++++++++++++++---------- > 1 file changed, 46 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index f2eca0db47fd..2198448fdb27 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1142,9 +1142,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct > intel_dp *intel_dp, > return false; > } > > - if (psr2_su_region_et_valid(intel_dp)) > - crtc_state->enable_psr2_su_region_et = true; > - > return crtc_state->enable_psr2_sel_fetch = true; } > > @@ -1515,11 +1512,6 @@ static bool intel_psr2_config_valid(struct intel_dp > *intel_dp, > return false; > } > > - if (!psr2_global_enabled(intel_dp)) { > - drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); > - return false; > - } > - > /* > * DSC and PSR2 cannot be enabled simultaneously. If a requested > * resolution requires DSC to be enabled, priority is given to DSC @@ > -1532,12 +1524,6 @@ static bool intel_psr2_config_valid(struct intel_dp > *intel_dp, > return false; > } > > - if (crtc_state->crc_enabled) { > - drm_dbg_kms(&dev_priv->drm, > - "PSR2 not enabled because it would inhibit pipe > CRC calculation\n"); > - return false; > - } > - > if (DISPLAY_VER(dev_priv) >= 12) { > psr_max_h = 5120; > psr_max_v = 3200; > @@ -1588,30 +1574,60 @@ static bool intel_psr2_config_valid(struct > intel_dp *intel_dp, > return false; > } > > - if (HAS_PSR2_SEL_FETCH(dev_priv)) { > - if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && > - !HAS_PSR_HW_TRACKING(dev_priv)) { > - drm_dbg_kms(&dev_priv->drm, > - "PSR2 not enabled, selective fetch not valid > and no HW tracking available\n"); > - return false; > - } > - } > - > - if (!psr2_granularity_check(intel_dp, crtc_state)) { > - drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU > granularity not compatible\n"); > - goto unsupported; > - } > - > if (!crtc_state->enable_psr2_sel_fetch && > (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { > drm_dbg_kms(&dev_priv->drm, > "PSR2 not enabled, resolution %dx%d > max > supported %dx%d\n", > crtc_hdisplay, crtc_vdisplay, > psr_max_h, psr_max_v); > - goto unsupported; > + return false; > } > > tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); > + > + if (psr2_su_region_et_valid(intel_dp)) > + crtc_state->enable_psr2_su_region_et = true; > + > + return true; > +} > + > +static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, > + struct intel_crtc_state *crtc_state) { > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + > + if (HAS_PSR2_SEL_FETCH(dev_priv) && > + !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && > + !HAS_PSR_HW_TRACKING(dev_priv)) { > + drm_dbg_kms(&dev_priv->drm, > + "Selective update not enabled, selective fetch not > valid and no HW tracking available\n"); > + goto unsupported; > + } > + > + if (!psr2_global_enabled(intel_dp)) { > + drm_dbg_kms(&dev_priv->drm, "Selective update disabled > by flag\n"); > + goto unsupported; > + } > + > + if (!crtc_state->has_panel_replay && > !intel_psr2_config_valid(intel_dp, crtc_state)) > + goto unsupported; > + > + if (crtc_state->has_panel_replay && (DISPLAY_VER(dev_priv) < 14 || > + !intel_dp- > >psr.sink_panel_replay_su_support)) > + goto unsupported; > + > + if (crtc_state->crc_enabled) { > + drm_dbg_kms(&dev_priv->drm, > + "Selective update not enabled because it would > inhibit pipe CRC calculation\n"); > + goto unsupported; > + } > + > + if (!psr2_granularity_check(intel_dp, crtc_state)) { > + drm_dbg_kms(&dev_priv->drm, > + "Selective update not enabled, SU granularity not > compatible\n"); > + goto unsupported; > + } > + > return true; > > unsupported: > @@ -1693,7 +1709,7 @@ void intel_psr_compute_config(struct intel_dp > *intel_dp, > if (!crtc_state->has_psr) > return; > > - crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, > crtc_state); > + crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, > +crtc_state); > } > > void intel_psr_get_config(struct intel_encoder *encoder, > -- > 2.34.1
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f2eca0db47fd..2198448fdb27 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1142,9 +1142,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, return false; } - if (psr2_su_region_et_valid(intel_dp)) - crtc_state->enable_psr2_su_region_et = true; - return crtc_state->enable_psr2_sel_fetch = true; } @@ -1515,11 +1512,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (!psr2_global_enabled(intel_dp)) { - drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); - return false; - } - /* * DSC and PSR2 cannot be enabled simultaneously. If a requested * resolution requires DSC to be enabled, priority is given to DSC @@ -1532,12 +1524,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (crtc_state->crc_enabled) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); - return false; - } - if (DISPLAY_VER(dev_priv) >= 12) { psr_max_h = 5120; psr_max_v = 3200; @@ -1588,30 +1574,60 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (HAS_PSR2_SEL_FETCH(dev_priv)) { - if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && - !HAS_PSR_HW_TRACKING(dev_priv)) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); - return false; - } - } - - if (!psr2_granularity_check(intel_dp, crtc_state)) { - drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); - goto unsupported; - } - if (!crtc_state->enable_psr2_sel_fetch && (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", crtc_hdisplay, crtc_vdisplay, psr_max_h, psr_max_v); - goto unsupported; + return false; } tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); + + if (psr2_su_region_et_valid(intel_dp)) + crtc_state->enable_psr2_su_region_et = true; + + return true; +} + +static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + if (HAS_PSR2_SEL_FETCH(dev_priv) && + !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && + !HAS_PSR_HW_TRACKING(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, + "Selective update not enabled, selective fetch not valid and no HW tracking available\n"); + goto unsupported; + } + + if (!psr2_global_enabled(intel_dp)) { + drm_dbg_kms(&dev_priv->drm, "Selective update disabled by flag\n"); + goto unsupported; + } + + if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state)) + goto unsupported; + + if (crtc_state->has_panel_replay && (DISPLAY_VER(dev_priv) < 14 || + !intel_dp->psr.sink_panel_replay_su_support)) + goto unsupported; + + if (crtc_state->crc_enabled) { + drm_dbg_kms(&dev_priv->drm, + "Selective update not enabled because it would inhibit pipe CRC calculation\n"); + goto unsupported; + } + + if (!psr2_granularity_check(intel_dp, crtc_state)) { + drm_dbg_kms(&dev_priv->drm, + "Selective update not enabled, SU granularity not compatible\n"); + goto unsupported; + } + return true; unsupported: @@ -1693,7 +1709,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (!crtc_state->has_psr) return; - crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, crtc_state); + crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); } void intel_psr_get_config(struct intel_encoder *encoder,
Part of intel_psr2_config_valid is valid for panel replay. rename it as intel_sel_update_config_valid. Split psr2 specific part and name it as intel_psr2_config_valid. v3: - move early transport check to psr2 specific check - check intel_psr2_config_valid only for non-Panel Replay case v2: - use psr2_global_enabled for panel replay as well - goto unsupported instead of return when global enabled check fails Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 76 ++++++++++++++---------- 1 file changed, 46 insertions(+), 30 deletions(-)