diff mbox series

[1/3] dt-bindings: phy: airoha: Add binding doc for PCIe PHY driver

Message ID 7b60943ea9814a1a9a3d8b273157b338f9130174.1715527166.git.lorenzo@kernel.org
State Superseded
Headers show
Series Introduce PCIe PHY driver for EN7581 SoC | expand

Commit Message

Lorenzo Bianconi May 12, 2024, 3:27 p.m. UTC 
Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY
driver.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 .../bindings/phy/airoha,pcie-phy.yaml         | 55 +++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml

Comments

AngeloGioacchino Del Regno May 13, 2024, 1:14 p.m. UTC | #1 
Il 12/05/24 17:27, Lorenzo Bianconi ha scritto:
> Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY
> driver.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>   .../bindings/phy/airoha,pcie-phy.yaml         | 55 +++++++++++++++++++
>   1 file changed, 55 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml
> new file mode 100644
> index 000000000000..443d7e717296
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml

airoha,en7581-pcie-phy.yaml

> @@ -0,0 +1,55 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/airoha,pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Airoha PCIe PHY

title: Airoha EN7581 PCI-Express PHY

> +
> +maintainers:
> +  - Lorenzo Bianconi <lorenzo@kernel.org>
> +
> +description: |
> +  The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
> +
> +properties:
> +  compatible:
> +    const: airoha,en7581-pcie-phy
> +
> +  reg:
> +    maxItems: 3
> +
> +  reg-names:
> +    items:
> +      - const: csr_2l
> +      - const: pma0
> +      - const: pma1
> +
> +  "#phy-cells":
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/phy/phy.h>
> +
> +    bus {

Shouldn't this realistically be 'soc' instead?

Cheers,
Angelo

> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        phy@11e80000 {
> +            compatible = "airoha,en7581-pcie-phy";
> +            #phy-cells = <0>;
> +            reg = <0x0 0x1fa5a000 0x0 0xfff>,
> +                  <0x0 0x1fa5b000 0x0 0xfff>,
> +                  <0x0 0x1fa5c000 0x0 0xfff>;
> +            reg-names = "csr_2l", "pma0", "pma1";
> +        };
> +    };
Conor Dooley May 13, 2024, 4:11 p.m. UTC | #2 
On Mon, May 13, 2024 at 03:14:59PM +0200, AngeloGioacchino Del Regno wrote:
> Il 12/05/24 17:27, Lorenzo Bianconi ha scritto:

> > +description: |
> > +  The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.

Additionally, the | here isn't needed cos there's no formatting to
preserve.
Lorenzo Bianconi May 13, 2024, 4:54 p.m. UTC | #3 
> Il 12/05/24 17:27, Lorenzo Bianconi ha scritto:
> > Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY
> > driver.
> > 
> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >   .../bindings/phy/airoha,pcie-phy.yaml         | 55 +++++++++++++++++++
> >   1 file changed, 55 insertions(+)
> >   create mode 100644 Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml
> > new file mode 100644
> > index 000000000000..443d7e717296
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml
> 
> airoha,en7581-pcie-phy.yaml

ack, I will fix it.

> 
> > @@ -0,0 +1,55 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/airoha,pcie-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Airoha PCIe PHY
> 
> title: Airoha EN7581 PCI-Express PHY

ack, I will fix it.

> 
> > +
> > +maintainers:
> > +  - Lorenzo Bianconi <lorenzo@kernel.org>
> > +
> > +description: |
> > +  The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
> > +
> > +properties:
> > +  compatible:
> > +    const: airoha,en7581-pcie-phy
> > +
> > +  reg:
> > +    maxItems: 3
> > +
> > +  reg-names:
> > +    items:
> > +      - const: csr_2l
> > +      - const: pma0
> > +      - const: pma1
> > +
> > +  "#phy-cells":
> > +    const: 0
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +  - "#phy-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/phy/phy.h>
> > +
> > +    bus {
> 
> Shouldn't this realistically be 'soc' instead?

ack, I will fix it.

Regards,
Lorenzo

> 
> Cheers,
> Angelo
> 
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        phy@11e80000 {
> > +            compatible = "airoha,en7581-pcie-phy";
> > +            #phy-cells = <0>;
> > +            reg = <0x0 0x1fa5a000 0x0 0xfff>,
> > +                  <0x0 0x1fa5b000 0x0 0xfff>,
> > +                  <0x0 0x1fa5c000 0x0 0xfff>;
> > +            reg-names = "csr_2l", "pma0", "pma1";
> > +        };
> > +    };
> 
> 
>
Lorenzo Bianconi May 13, 2024, 4:55 p.m. UTC | #4 
> On Mon, May 13, 2024 at 03:14:59PM +0200, AngeloGioacchino Del Regno wrote:
> > Il 12/05/24 17:27, Lorenzo Bianconi ha scritto:
> 
> > > +description: |
> > > +  The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
> 
> Additionally, the | here isn't needed cos there's no formatting to
> preserve.

ack, I will fix it in v2.

Regards,
Lorenzo
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml
new file mode 100644
index 000000000000..443d7e717296
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml
@@ -0,0 +1,55 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/airoha,pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha PCIe PHY
+
+maintainers:
+  - Lorenzo Bianconi <lorenzo@kernel.org>
+
+description: |
+  The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
+
+properties:
+  compatible:
+    const: airoha,en7581-pcie-phy
+
+  reg:
+    maxItems: 3
+
+  reg-names:
+    items:
+      - const: csr_2l
+      - const: pma0
+      - const: pma1
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/phy/phy.h>
+
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        phy@11e80000 {
+            compatible = "airoha,en7581-pcie-phy";
+            #phy-cells = <0>;
+            reg = <0x0 0x1fa5a000 0x0 0xfff>,
+                  <0x0 0x1fa5b000 0x0 0xfff>,
+                  <0x0 0x1fa5c000 0x0 0xfff>;
+            reg-names = "csr_2l", "pma0", "pma1";
+        };
+    };