Message ID | 20240515050253.38061-1-joshua.yeong@starfivetech.com (mailing list archive) |
---|---|
Headers | show |
Series | Add StarFive's StarLink Cache Controller | expand |
On Wed, May 15, 2024 at 01:02:51PM +0800, Joshua Yeong wrote: > StarFive's StarLink Cache Controller flush/invalidates cache using non- > conventional RISC-V Zicbom extension instructions. This driver provides the > cache handling on StarFive RISC-V SoC. > > Changes in v4: > - Move cache controller initialization to arch_initcall() > - Link to v3: https://lore.kernel.org/all/20240424075856.145850-1-joshua.yeong@starfivetech.com/ Why are you resending this? A resend with no context doesn't help me understand what you want done. There's been no action taken yet with the v4 that you had sent because there was not enough time between its arrival and when I had to send a PR with 6.10 material. Right now it is the merge window, so there's nothing that can be done here til that ends. Cheers, Conor.
From: Conor Dooley <conor.dooley@microchip.com> On Wed, 15 May 2024 13:02:51 +0800, Joshua Yeong wrote: > StarFive's StarLink Cache Controller flush/invalidates cache using non- > conventional RISC-V Zicbom extension instructions. This driver provides the > cache handling on StarFive RISC-V SoC. > > Changes in v4: > - Move cache controller initialization to arch_initcall() > - Link to v3: https://lore.kernel.org/all/20240424075856.145850-1-joshua.yeong@starfivetech.com/ > > [...] I've picked these two up and applied to riscv-cache-for-next, with their order corrected. Emil, shout if there was something left from your feedback that was unimplemented. The wording etc seems to have been "fixed" in this version. [1/2] cache: Add StarFive StarLink cache management https://git.kernel.org/conor/c/cabff60ca77d [2/2] dt-bindings: cache: Add docs for StarFive Starlink cache controller https://git.kernel.org/conor/c/c6005d4dd216 Thanks, Conor.