| Message ID | 20240521013029.30082-8-npiggin@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/ppc: Various TCG emulation patches | expand |
Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR > means > per-thread or per-core, depending on 1LPAR mode. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- > target/ppc/spr_common.h | 2 ++ > target/ppc/translate.c | 28 ++++++++++++++++++++++++++++ > 2 files changed, 30 insertions(+) > > diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h > index 9e40b3b608..85f73b860b 100644 > --- a/target/ppc/spr_common.h > +++ b/target/ppc/spr_common.h > @@ -83,6 +83,8 @@ void spr_read_generic(DisasContext *ctx, int gprn, > int sprn); > void spr_write_generic(DisasContext *ctx, int sprn, int gprn); > void spr_write_generic32(DisasContext *ctx, int sprn, int gprn); > void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn); > +void spr_core_write_generic32(DisasContext *ctx, int sprn, int > gprn); > +void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int > gprn); > void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); > void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn); > void spr_write_MMCRA(DisasContext *ctx, int sprn, int gprn); > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 137370b649..c688551434 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -535,6 +535,34 @@ void spr_core_write_generic(DisasContext *ctx, > int sprn, int gprn) > spr_store_dump_spr(sprn); > } > > +void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn) > +{ > + TCGv t0; > + > + if (!(ctx->flags & POWERPC_FLAG_SMT)) { > + spr_write_generic32(ctx, sprn, gprn); > + return; > + } > + > + if (!gen_serialize(ctx)) { > + return; > + } > + > + t0 = tcg_temp_new(); > + tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); > + gen_helper_spr_core_write_generic(tcg_env, > tcg_constant_i32(sprn), t0); > + spr_store_dump_spr(sprn); > +} > + > +void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int > gprn) > +{ > + if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { > + spr_core_write_generic(ctx, sprn, gprn); > + } else { > + spr_write_generic(ctx, sprn, gprn); > + } > +} > + > static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) > { > /* This does not implement >1 thread */
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index 9e40b3b608..85f73b860b 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -83,6 +83,8 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_generic32(DisasContext *ctx, int sprn, int gprn); void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn); +void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn); +void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCRA(DisasContext *ctx, int sprn, int gprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 137370b649..c688551434 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -535,6 +535,34 @@ void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) spr_store_dump_spr(sprn); } +void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0; + + if (!(ctx->flags & POWERPC_FLAG_SMT)) { + spr_write_generic32(ctx, sprn, gprn); + return; + } + + if (!gen_serialize(ctx)) { + return; + } + + t0 = tcg_temp_new(); + tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); + gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), t0); + spr_store_dump_spr(sprn); +} + +void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn) +{ + if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { + spr_core_write_generic(ctx, sprn, gprn); + } else { + spr_write_generic(ctx, sprn, gprn); + } +} + static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) { /* This does not implement >1 thread */
An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means per-thread or per-core, depending on 1LPAR mode. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- target/ppc/spr_common.h | 2 ++ target/ppc/translate.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+)