| Message ID | CACqvRUbx-KsrMwCHYQS6eGXBohynD8Q1CQx=8=9VhqZi13BCQQ@mail.gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | net: mdio: meson-gxl set 28th bit in eth_reg2 | expand |
On Tue, May 21, 2024 at 02:56:45PM -0400, Da Xue wrote: > This bit is necessary to enable packets on the interface. Without this > bit set, ethernet behaves as if it is working but no activity occurs. > > The vendor SDK sets this bit along with the PHY_ID bits. u-boot will set > this bit as well but if u-boot is not compiled with networking, the > interface will not work. > > Fixes: 9a24e1ff4326 ("net: mdio: add amlogic gxl mdio mux support"); > > Signed-off-by: Da Xue <da@libre.computer> Please don't put blank lines between tags. If you intend that this patch is backported to stable, please add Cc: stable@vger.kernel.org Also please read: https://www.kernel.org/doc/html/latest/process/maintainer-netdev.html#netdev-faq particularly the bit about indicating the tree in the Subject: Andrew --- pw-bot: cr
On Tue, May 21, 2024 at 02:56:45PM -0400, Da Xue wrote: > @@ -65,7 +66,7 @@ static void gxl_enable_internal_mdio(struct > gxl_mdio_mux *priv) > * The only constraint is that it must match the one in > * drivers/net/phy/meson-gxl.c to properly match the PHY. > */ > - writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), > + writel(REG2_RESERVED_28 | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), > priv->regs + ETH_REG2); > > /* Enable the internal phy */ In addition to what Andrew said, you need to look at how you're sending patches - this patch looks like it has been whitespace damaged, which means it can't be applied.
On Tue, May 21, 2024 at 3:24 PM Russell King (Oracle) <linux@armlinux.org.uk> wrote: > > On Tue, May 21, 2024 at 02:56:45PM -0400, Da Xue wrote: > > @@ -65,7 +66,7 @@ static void gxl_enable_internal_mdio(struct > > gxl_mdio_mux *priv) > > * The only constraint is that it must match the one in > > * drivers/net/phy/meson-gxl.c to properly match the PHY. > > */ > > - writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), > > + writel(REG2_RESERVED_28 | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), > > priv->regs + ETH_REG2); > > > > /* Enable the internal phy */ > > In addition to what Andrew said, you need to look at how you're sending > patches - this patch looks like it has been whitespace damaged, which > means it can't be applied. Thanks for the feedback. There's 2 reserved ranges in that register with no further descriptions available. If naming the bit offset after the field range is OK, I will make edit and submit a V2 though send-email. > > -- > RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ > FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
diff --git a/drivers/net/mdio/mdio-mux-meson-gxl.c b/drivers/net/mdio/mdio-mux-meson-gxl.c index 89554021b5cc..b2bd57f54034 100644 --- a/drivers/net/mdio/mdio-mux-meson-gxl.c +++ b/drivers/net/mdio/mdio-mux-meson-gxl.c @@ -17,6 +17,7 @@ #define REG2_LEDACT GENMASK(23, 22) #define REG2_LEDLINK GENMASK(25, 24) #define REG2_DIV4SEL BIT(27) +#define REG2_RESERVED_28 BIT(28) #define REG2_ADCBYPASS BIT(30) #define REG2_CLKINSEL BIT(31) #define ETH_REG3 0x4 @@ -65,7 +66,7 @@ static void gxl_enable_internal_mdio(struct gxl_mdio_mux *priv) * The only constraint is that it must match the one in * drivers/net/phy/meson-gxl.c to properly match the PHY. */ - writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), + writel(REG2_RESERVED_28 | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), priv->regs + ETH_REG2);
This bit is necessary to enable packets on the interface. Without this bit set, ethernet behaves as if it is working but no activity occurs. The vendor SDK sets this bit along with the PHY_ID bits. u-boot will set this bit as well but if u-boot is not compiled with networking, the interface will not work. Fixes: 9a24e1ff4326 ("net: mdio: add amlogic gxl mdio mux support"); Signed-off-by: Da Xue <da@libre.computer> --- drivers/net/mdio/mdio-mux-meson-gxl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) /* Enable the internal phy */