| Message ID | 20240520145402.2526481-7-sean.anderson@linux.dev (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: xilinx-nwl: Add phy support | expand |
> Add support for enabling/disabling PCIe phys. We can't really do > anything about failures in the disable/remove path, so just warn. … > +++ b/drivers/pci/controller/pcie-xilinx-nwl.c … > @@ -818,12 +876,15 @@ static int nwl_pcie_probe(struct platform_device *pdev) > err = nwl_pcie_enable_msi(pcie); > if (err < 0) { > dev_err(dev, "failed to enable MSI support: %d\n", err); > - goto err_clk; > + goto err_phy; > } > } > > err = pci_host_probe(bridge); > > +err_phy: > + if (err) > + nwl_pcie_phy_disable(pcie); > err_clk: > if (err) > clk_disable_unprepare(pcie->clk); I got the impression that some source code adjustments should be performed in another separate update step for this function implementation. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n81 You propose to extend the exception handling here. Does such information indicate a need for another tag “Fixes”? How do you think about to increase the usage of a corresponding goto chain? https://wiki.sei.cmu.edu/confluence/display/c/MEM12-C.+Consider+using+a+goto+chain+when+leaving+a+function+on+error+when+using+and+releasing+resources Would you become more interested in the application of scope-based resource management? Regards, Markus
On 5/24/24 04:16, Markus Elfring wrote: >> Add support for enabling/disabling PCIe phys. We can't really do >> anything about failures in the disable/remove path, so just warn. > … >> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c > … >> @@ -818,12 +876,15 @@ static int nwl_pcie_probe(struct platform_device *pdev) >> err = nwl_pcie_enable_msi(pcie); >> if (err < 0) { >> dev_err(dev, "failed to enable MSI support: %d\n", err); >> - goto err_clk; >> + goto err_phy; >> } >> } >> >> err = pci_host_probe(bridge); >> >> +err_phy: >> + if (err) >> + nwl_pcie_phy_disable(pcie); >> err_clk: >> if (err) >> clk_disable_unprepare(pcie->clk); > > I got the impression that some source code adjustments should be performed > in another separate update step for this function implementation. > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n81 > > You propose to extend the exception handling here. > Does such information indicate a need for another tag “Fixes”? Huh? I am only disabling what I enabled... --Sean
On Mon, May 20, 2024 at 10:54:01AM -0400, Sean Anderson wrote: > +static int nwl_pcie_phy_enable(struct nwl_pcie *pcie) > +{ > + int i, ret; > + > + for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { > + ret = phy_init(pcie->phy[i]); > + if (ret) > + goto err; > + > + ret = phy_power_on(pcie->phy[i]); > + if (ret) { > + WARN_ON(phy_exit(pcie->phy[i])); > + goto err; > + } > + } > + > + return 0; > + > +err: > + while (--i) { This doesn't work. If we fail on the first iteration, then it will lead to an array underflow. It should be while (--i >= 0) or while (i--). I prefer the first, but the second format works for people who use unsigned iterators. > + WARN_ON(phy_power_off(pcie->phy[i])); > + WARN_ON(phy_exit(pcie->phy[i])); > + } > + > + return ret; > +} regards, dan carpenter
On 5/24/24 10:59, Dan Carpenter wrote: > On Mon, May 20, 2024 at 10:54:01AM -0400, Sean Anderson wrote: >> +static int nwl_pcie_phy_enable(struct nwl_pcie *pcie) >> +{ >> + int i, ret; >> + >> + for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { >> + ret = phy_init(pcie->phy[i]); >> + if (ret) >> + goto err; >> + >> + ret = phy_power_on(pcie->phy[i]); >> + if (ret) { >> + WARN_ON(phy_exit(pcie->phy[i])); >> + goto err; >> + } >> + } >> + >> + return 0; >> + >> +err: >> + while (--i) { > > This doesn't work. If we fail on the first iteration, then it will > lead to an array underflow. It should be while (--i >= 0) or > while (i--). I prefer the first, but the second format works for people > who use unsigned iterators. Thanks, will fix. --Sean >> + WARN_ON(phy_power_off(pcie->phy[i])); >> + WARN_ON(phy_exit(pcie->phy[i])); >> + } >> + >> + return ret; >> +} > > regards, > dan carpenter >
>> … >>> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c >> … >>> @@ -818,12 +876,15 @@ static int nwl_pcie_probe(struct platform_device *pdev) >>> err = nwl_pcie_enable_msi(pcie); >>> if (err < 0) { >>> dev_err(dev, "failed to enable MSI support: %d\n", err); >>> - goto err_clk; >>> + goto err_phy; >>> } >>> } >>> >>> err = pci_host_probe(bridge); >>> >>> +err_phy: >>> + if (err) >>> + nwl_pcie_phy_disable(pcie); >>> err_clk: >>> if (err) >>> clk_disable_unprepare(pcie->clk); >> >> I got the impression that some source code adjustments should be performed >> in another separate update step for this function implementation. >> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.9#n81 >> >> You propose to extend the exception handling here. >> Does such information indicate a need for another tag “Fixes”? > > Huh? I am only disabling what I enabled... * Was a resource deactivation accidentally missing in a previous release of this software component? * Can repeated checks be avoided a bit more by a design approach which we tried to clarify for the update step “[PATCH v3 5/7] PCI: xilinx-nwl: Clean up clock on probe failure/removal”? https://lore.kernel.org/lkml/bb9e239f-902b-4f52-a5e9-98c29b360418@linux.dev/ Regards, Markus
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 424cc5a1b4d1..d32cf4247836 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -19,6 +19,7 @@ #include <linux/of_platform.h> #include <linux/pci.h> #include <linux/pci-ecam.h> +#include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/irqchip/chained_irq.h> @@ -157,6 +158,7 @@ struct nwl_pcie { void __iomem *breg_base; void __iomem *pcireg_base; void __iomem *ecam_base; + struct phy *phy[4]; phys_addr_t phys_breg_base; /* Physical Bridge Register Base */ phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */ phys_addr_t phys_ecam_base; /* Physical Configuration Base */ @@ -521,6 +523,43 @@ static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) return 0; } +static int nwl_pcie_phy_enable(struct nwl_pcie *pcie) +{ + int i, ret; + + for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { + ret = phy_init(pcie->phy[i]); + if (ret) + goto err; + + ret = phy_power_on(pcie->phy[i]); + if (ret) { + WARN_ON(phy_exit(pcie->phy[i])); + goto err; + } + } + + return 0; + +err: + while (--i) { + WARN_ON(phy_power_off(pcie->phy[i])); + WARN_ON(phy_exit(pcie->phy[i])); + } + + return ret; +} + +static void nwl_pcie_phy_disable(struct nwl_pcie *pcie) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { + WARN_ON(phy_power_off(pcie->phy[i])); + WARN_ON(phy_exit(pcie->phy[i])); + } +} + static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) { struct device *dev = pcie->dev; @@ -732,6 +771,7 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, { struct device *dev = pcie->dev; struct resource *res; + int i; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); pcie->breg_base = devm_ioremap_resource(dev, res); @@ -759,6 +799,18 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, irq_set_chained_handler_and_data(pcie->irq_intx, nwl_pcie_leg_handler, pcie); + + for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { + pcie->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i); + if (PTR_ERR(pcie->phy[i]) == -ENODEV) { + pcie->phy[i] = NULL; + break; + } + + if (IS_ERR(pcie->phy[i])) + return PTR_ERR(pcie->phy[i]); + } + return 0; } @@ -799,16 +851,22 @@ static int nwl_pcie_probe(struct platform_device *pdev) return err; } + err = nwl_pcie_phy_enable(pcie); + if (err) { + dev_err(dev, "could not enable PHYs\n"); + goto err_clk; + } + err = nwl_pcie_bridge_init(pcie); if (err) { dev_err(dev, "HW Initialization failed\n"); - goto err_clk; + goto err_phy; } err = nwl_pcie_init_irq_domain(pcie); if (err) { dev_err(dev, "Failed creating IRQ Domain\n"); - goto err_clk; + goto err_phy; } bridge->sysdata = pcie; @@ -818,12 +876,15 @@ static int nwl_pcie_probe(struct platform_device *pdev) err = nwl_pcie_enable_msi(pcie); if (err < 0) { dev_err(dev, "failed to enable MSI support: %d\n", err); - goto err_clk; + goto err_phy; } } err = pci_host_probe(bridge); +err_phy: + if (err) + nwl_pcie_phy_disable(pcie); err_clk: if (err) clk_disable_unprepare(pcie->clk); @@ -834,6 +895,7 @@ static void nwl_pcie_remove(struct platform_device *pdev) { struct nwl_pcie *pcie = platform_get_drvdata(pdev); + nwl_pcie_phy_disable(pcie); clk_disable_unprepare(pcie->clk); }
Add support for enabling/disabling PCIe phys. We can't really do anything about failures in the disable/remove path, so just warn. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> --- (no changes since v2) Changes in v2: - Get phys by index and not by name drivers/pci/controller/pcie-xilinx-nwl.c | 68 ++++++++++++++++++++++-- 1 file changed, 65 insertions(+), 3 deletions(-)