| Message ID | 20240515091129.28116-1-yongxuan.wang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA | expand |
On Wed, May 15, 2024 at 05:11:28PM GMT, Yong-Xuan Wang wrote: > In AIA spec, each hart (or each hart within a group) has a unique hart > number to locate the memory pages of interrupt files in the address > space. The number of bits required to represent any hart number is equal > to ceil(log2(hmax + 1)), where hmax is the largest hart number among > groups. > > However, if the largest hart number among groups is a power of 2, QEMU > will pass an inaccurate hart-index-bit setting to Linux. For example, when > the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient > to represent 4 harts, but we passes 3 to Linux. The code needs to be > updated to ensure accurate hart-index-bit settings. > > Additionally, a Linux patch[1] is necessary to correctly recover the hart > index when the guest OS has only 1 hart, where the hart-index-bit is 0. > > [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/ > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> > --- > Changelog > v2: > - update commit message > --- > target/riscv/kvm/kvm-cpu.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 473416649fda..235e2cdaca1a 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -1777,7 +1777,14 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, > } > } > > - hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; > + > + if (max_hart_per_socket > 1) { > + max_hart_per_socket--; > + hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; > + } else { > + hart_bits = 0; > + } > + > ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, > KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, > &hart_bits, true, NULL); > -- > 2.17.1 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
On Wed, May 15, 2024 at 7:12 PM Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote: > > In AIA spec, each hart (or each hart within a group) has a unique hart > number to locate the memory pages of interrupt files in the address > space. The number of bits required to represent any hart number is equal > to ceil(log2(hmax + 1)), where hmax is the largest hart number among > groups. > > However, if the largest hart number among groups is a power of 2, QEMU > will pass an inaccurate hart-index-bit setting to Linux. For example, when > the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient > to represent 4 harts, but we passes 3 to Linux. The code needs to be > updated to ensure accurate hart-index-bit settings. > > Additionally, a Linux patch[1] is necessary to correctly recover the hart > index when the guest OS has only 1 hart, where the hart-index-bit is 0. > > [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/ > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > Changelog > v2: > - update commit message > --- > target/riscv/kvm/kvm-cpu.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 473416649fda..235e2cdaca1a 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -1777,7 +1777,14 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, > } > } > > - hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; > + > + if (max_hart_per_socket > 1) { > + max_hart_per_socket--; > + hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; > + } else { > + hart_bits = 0; > + } > + > ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, > KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, > &hart_bits, true, NULL); > -- > 2.17.1 > >
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 473416649fda..235e2cdaca1a 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1777,7 +1777,14 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, } } - hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; + + if (max_hart_per_socket > 1) { + max_hart_per_socket--; + hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; + } else { + hart_bits = 0; + } + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, &hart_bits, true, NULL);
In AIA spec, each hart (or each hart within a group) has a unique hart number to locate the memory pages of interrupt files in the address space. The number of bits required to represent any hart number is equal to ceil(log2(hmax + 1)), where hmax is the largest hart number among groups. However, if the largest hart number among groups is a power of 2, QEMU will pass an inaccurate hart-index-bit setting to Linux. For example, when the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient to represent 4 harts, but we passes 3 to Linux. The code needs to be updated to ensure accurate hart-index-bit settings. Additionally, a Linux patch[1] is necessary to correctly recover the hart index when the guest OS has only 1 hart, where the hart-index-bit is 0. [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/ Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> --- Changelog v2: - update commit message --- target/riscv/kvm/kvm-cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)