| Message ID | 20240408172315.3418692-1-jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/i915: move rawclk init to intel_cdclk_init() | expand |
On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote: > The rawclk initialization is a bit out of place in > intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a > bit of refactoring on intel_read_rawclk(). rawclk is used outside of display. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++----------- > drivers/gpu/drm/i915/display/intel_cdclk.h | 1 - > drivers/gpu/drm/i915/intel_device_info.c | 4 ---- > 3 files changed, 11 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index d61aa5b7cbdb..64a1cf4ed45c 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -3210,6 +3210,8 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi > return intel_atomic_lock_global_state(&cdclk_state->base); > } > > +static void intel_rawclk_init(struct drm_i915_private *dev_priv); > + > int intel_cdclk_init(struct drm_i915_private *dev_priv) > { > struct intel_cdclk_state *cdclk_state; > @@ -3221,6 +3223,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv) > intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, > &cdclk_state->base, &intel_cdclk_funcs); > > + intel_rawclk_init(dev_priv); > + > return 0; > } > > @@ -3578,16 +3582,13 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv) > } > } > > -/** > - * intel_read_rawclk - Determine the current RAWCLK frequency > - * @dev_priv: i915 device > - * > - * Determine the current RAWCLK frequency. RAWCLK is a fixed > - * frequency clock so this needs to done only once. > +/* > + * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency clock so > + * this needs to done only once. > */ > -u32 intel_read_rawclk(struct drm_i915_private *dev_priv) > +static void intel_rawclk_init(struct drm_i915_private *dev_priv) > { > - u32 freq; > + u32 freq = 0; > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) > /* > @@ -3606,11 +3607,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) > freq = vlv_hrawclk(dev_priv); > else if (DISPLAY_VER(dev_priv) >= 3) > freq = i9xx_hrawclk(dev_priv); > - else > - /* no rawclk on other platforms, or no need to know it */ > - return 0; > > - return freq; > + RUNTIME_INFO(dev_priv)->rawclk_freq = freq; > + drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq); > } > > static int i915_cdclk_info_show(struct seq_file *m, void *unused) > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h > index cfdcdec07a4d..a3f950d5a366 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.h > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h > @@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915); > void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); > void intel_update_max_cdclk(struct drm_i915_private *dev_priv); > void intel_update_cdclk(struct drm_i915_private *dev_priv); > -u32 intel_read_rawclk(struct drm_i915_private *dev_priv); > bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, > const struct intel_cdclk_config *b); > int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915, > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index a0a43ea07f11..48f0957392f9 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > "Disabling ppGTT for VT-d support\n"); > runtime->ppgtt_type = INTEL_PPGTT_NONE; > } > - > - runtime->rawclk_freq = intel_read_rawclk(dev_priv); > - drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); > - > } > > /* > -- > 2.39.2
On Mon, Apr 08, 2024 at 08:28:27PM +0300, Ville Syrjälä wrote: > On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote: > > The rawclk initialization is a bit out of place in > > intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a > > bit of refactoring on intel_read_rawclk(). > > rawclk is used outside of display. The correct solution would likely be to extract a i9xx_fsb_freq(), and use that to populate both rawclk_freq and fsb_freq (and switch over to fsb_freq in the non-display code). > > > > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++----------- > > drivers/gpu/drm/i915/display/intel_cdclk.h | 1 - > > drivers/gpu/drm/i915/intel_device_info.c | 4 ---- > > 3 files changed, 11 insertions(+), 17 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > > index d61aa5b7cbdb..64a1cf4ed45c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > @@ -3210,6 +3210,8 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi > > return intel_atomic_lock_global_state(&cdclk_state->base); > > } > > > > +static void intel_rawclk_init(struct drm_i915_private *dev_priv); > > + > > int intel_cdclk_init(struct drm_i915_private *dev_priv) > > { > > struct intel_cdclk_state *cdclk_state; > > @@ -3221,6 +3223,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv) > > intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, > > &cdclk_state->base, &intel_cdclk_funcs); > > > > + intel_rawclk_init(dev_priv); > > + > > return 0; > > } > > > > @@ -3578,16 +3582,13 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv) > > } > > } > > > > -/** > > - * intel_read_rawclk - Determine the current RAWCLK frequency > > - * @dev_priv: i915 device > > - * > > - * Determine the current RAWCLK frequency. RAWCLK is a fixed > > - * frequency clock so this needs to done only once. > > +/* > > + * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency clock so > > + * this needs to done only once. > > */ > > -u32 intel_read_rawclk(struct drm_i915_private *dev_priv) > > +static void intel_rawclk_init(struct drm_i915_private *dev_priv) > > { > > - u32 freq; > > + u32 freq = 0; > > > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) > > /* > > @@ -3606,11 +3607,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) > > freq = vlv_hrawclk(dev_priv); > > else if (DISPLAY_VER(dev_priv) >= 3) > > freq = i9xx_hrawclk(dev_priv); > > - else > > - /* no rawclk on other platforms, or no need to know it */ > > - return 0; > > > > - return freq; > > + RUNTIME_INFO(dev_priv)->rawclk_freq = freq; > > + drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq); > > } > > > > static int i915_cdclk_info_show(struct seq_file *m, void *unused) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h > > index cfdcdec07a4d..a3f950d5a366 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.h > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h > > @@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915); > > void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); > > void intel_update_max_cdclk(struct drm_i915_private *dev_priv); > > void intel_update_cdclk(struct drm_i915_private *dev_priv); > > -u32 intel_read_rawclk(struct drm_i915_private *dev_priv); > > bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, > > const struct intel_cdclk_config *b); > > int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915, > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > > index a0a43ea07f11..48f0957392f9 100644 > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > @@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > > "Disabling ppGTT for VT-d support\n"); > > runtime->ppgtt_type = INTEL_PPGTT_NONE; > > } > > - > > - runtime->rawclk_freq = intel_read_rawclk(dev_priv); > > - drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); > > - > > } > > > > /* > > -- > > 2.39.2 > > -- > Ville Syrjälä > Intel
On Mon, 08 Apr 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Mon, Apr 08, 2024 at 08:28:27PM +0300, Ville Syrjälä wrote: >> On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote: >> > The rawclk initialization is a bit out of place in >> > intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a >> > bit of refactoring on intel_read_rawclk(). >> >> rawclk is used outside of display. > > The correct solution would likely be to extract a > i9xx_fsb_freq(), and use that to populate both rawclk_freq > and fsb_freq (and switch over to fsb_freq in the > non-display code). I circled back to this, and PNV seems to be the problem case for making this happen. pnv_detect_mem_freq() in intel_dram.c and i9xx_hrawclk() in intel_cdclk.c interpret the CLKCFG register slightly differently. I'm presuming PNV only supports a subset of the values covered by i9xx_hrawclk(). For IS_MOBILE() they all match, but for !IS_MOBILE() there's a different value for 400 MHz FSB. So how should desktop PNV interpret the register, I wonder? I can't find any specs on that anymore. BR, Jani.
On Mon, 27 May 2024, Jani Nikula <jani.nikula@intel.com> wrote: > On Mon, 08 Apr 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: >> On Mon, Apr 08, 2024 at 08:28:27PM +0300, Ville Syrjälä wrote: >>> On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote: >>> > The rawclk initialization is a bit out of place in >>> > intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a >>> > bit of refactoring on intel_read_rawclk(). >>> >>> rawclk is used outside of display. >> >> The correct solution would likely be to extract a >> i9xx_fsb_freq(), and use that to populate both rawclk_freq >> and fsb_freq (and switch over to fsb_freq in the >> non-display code). > > I circled back to this, and PNV seems to be the problem case for making > this happen. > > pnv_detect_mem_freq() in intel_dram.c and i9xx_hrawclk() in > intel_cdclk.c interpret the CLKCFG register slightly differently. > > I'm presuming PNV only supports a subset of the values covered by > i9xx_hrawclk(). For IS_MOBILE() they all match, but for !IS_MOBILE() > there's a different value for 400 MHz FSB. > > So how should desktop PNV interpret the register, I wonder? I can't find > any specs on that anymore. My guess would be this: index b78154c82a71..19ca3ed5212a 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3545,7 +3545,7 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv) */ clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; - if (IS_MOBILE(dev_priv)) { + if (IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv)) { switch (clkcfg) { case CLKCFG_FSB_400: return 100000;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index d61aa5b7cbdb..64a1cf4ed45c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3210,6 +3210,8 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi return intel_atomic_lock_global_state(&cdclk_state->base); } +static void intel_rawclk_init(struct drm_i915_private *dev_priv); + int intel_cdclk_init(struct drm_i915_private *dev_priv) { struct intel_cdclk_state *cdclk_state; @@ -3221,6 +3223,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv) intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, &cdclk_state->base, &intel_cdclk_funcs); + intel_rawclk_init(dev_priv); + return 0; } @@ -3578,16 +3582,13 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv) } } -/** - * intel_read_rawclk - Determine the current RAWCLK frequency - * @dev_priv: i915 device - * - * Determine the current RAWCLK frequency. RAWCLK is a fixed - * frequency clock so this needs to done only once. +/* + * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency clock so + * this needs to done only once. */ -u32 intel_read_rawclk(struct drm_i915_private *dev_priv) +static void intel_rawclk_init(struct drm_i915_private *dev_priv) { - u32 freq; + u32 freq = 0; if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) /* @@ -3606,11 +3607,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) freq = vlv_hrawclk(dev_priv); else if (DISPLAY_VER(dev_priv) >= 3) freq = i9xx_hrawclk(dev_priv); - else - /* no rawclk on other platforms, or no need to know it */ - return 0; - return freq; + RUNTIME_INFO(dev_priv)->rawclk_freq = freq; + drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq); } static int i915_cdclk_info_show(struct seq_file *m, void *unused) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index cfdcdec07a4d..a3f950d5a366 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915); void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); void intel_update_max_cdclk(struct drm_i915_private *dev_priv); void intel_update_cdclk(struct drm_i915_private *dev_priv); -u32 intel_read_rawclk(struct drm_i915_private *dev_priv); bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b); int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index a0a43ea07f11..48f0957392f9 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) "Disabling ppGTT for VT-d support\n"); runtime->ppgtt_type = INTEL_PPGTT_NONE; } - - runtime->rawclk_freq = intel_read_rawclk(dev_priv); - drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); - } /*
The rawclk initialization is a bit out of place in intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a bit of refactoring on intel_read_rawclk(). Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++----------- drivers/gpu/drm/i915/display/intel_cdclk.h | 1 - drivers/gpu/drm/i915/intel_device_info.c | 4 ---- 3 files changed, 11 insertions(+), 17 deletions(-)