mbox series

[v4,0/2,RESEND] Add StarFive's StarLink Cache Controller

Message ID 20240515050253.38061-1-joshua.yeong@starfivetech.com (mailing list archive)
Headers show
Series Add StarFive's StarLink Cache Controller | expand

Message

Joshua Yeong May 15, 2024, 5:02 a.m. UTC
StarFive's StarLink Cache Controller flush/invalidates cache using non-
conventional RISC-V Zicbom extension instructions. This driver provides the
cache handling on StarFive RISC-V SoC.

Changes in v4:
- Move cache controller initialization to arch_initcall()
- Link to v3: https://lore.kernel.org/all/20240424075856.145850-1-joshua.yeong@starfivetech.com/

Changes in v3:
- Fix code syntax
- Link to v2: https://lore.kernel.org/all/20240423072639.143450-1-joshua.yeong@starfivetech.com/

Changes in v2:
- Change patch title from 'Add StarFive's StarLink-500 Cache Controller'
- Remove StarFive alternative from errata framework
- Fixes warning from https://lore.kernel.org/oe-kbuild-all/202403151625.boKDjHGr-lkp@intel.com/
- Flush completion through atomic timeout function
- Link to v1: https://lore.kernel.org/lkml/20240314061205.26143-1-joshua.yeong@starfivetech.com/

Joshua Yeong (2):
  cache: Add StarFive StarLink cache management for StarFive JH8100
  dt-bindings: cache: Add docs for StarFive Starlink cache controller

Joshua Yeong (2):
  cache: Add StarFive StarLink cache management
  dt-bindings: cache: Add docs for StarFive Starlink cache controller

 .../cache/starfive,jh8100-starlink-cache.yaml |  66 +++++++++
 drivers/cache/Kconfig                         |   9 ++
 drivers/cache/Makefile                        |   5 +-
 drivers/cache/starfive_starlink_cache.c       | 130 ++++++++++++++++++
 4 files changed, 208 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
 create mode 100644 drivers/cache/starfive_starlink_cache.c

--
2.25.1

Comments

Conor Dooley May 15, 2024, 7:21 a.m. UTC | #1
On Wed, May 15, 2024 at 01:02:51PM +0800, Joshua Yeong wrote:
> StarFive's StarLink Cache Controller flush/invalidates cache using non-
> conventional RISC-V Zicbom extension instructions. This driver provides the
> cache handling on StarFive RISC-V SoC.
> 
> Changes in v4:
> - Move cache controller initialization to arch_initcall()
> - Link to v3: https://lore.kernel.org/all/20240424075856.145850-1-joshua.yeong@starfivetech.com/

Why are you resending this? A resend with no context doesn't help me
understand what you want done.
There's been no action taken yet with the v4 that you had sent because
there was not enough time between its arrival and when I had to send a
PR with 6.10 material. Right now it is the merge window, so there's
nothing that can be done here til that ends.

Cheers,
Conor.
Conor Dooley May 28, 2024, 11:44 a.m. UTC | #2
From: Conor Dooley <conor.dooley@microchip.com>

On Wed, 15 May 2024 13:02:51 +0800, Joshua Yeong wrote:
> StarFive's StarLink Cache Controller flush/invalidates cache using non-
> conventional RISC-V Zicbom extension instructions. This driver provides the
> cache handling on StarFive RISC-V SoC.
> 
> Changes in v4:
> - Move cache controller initialization to arch_initcall()
> - Link to v3: https://lore.kernel.org/all/20240424075856.145850-1-joshua.yeong@starfivetech.com/
> 
> [...]

I've picked these two up and applied to riscv-cache-for-next, with their
order corrected. Emil, shout if there was something left from your
feedback that was unimplemented. The wording etc seems to have been
"fixed" in this version.

[1/2] cache: Add StarFive StarLink cache management
      https://git.kernel.org/conor/c/cabff60ca77d
[2/2] dt-bindings: cache: Add docs for StarFive Starlink cache controller
      https://git.kernel.org/conor/c/c6005d4dd216

Thanks,
Conor.