diff mbox series

[v3,7/7] arm64: dts: ti: k3-j722s: Add support for PCIe0

Message ID 20240524090514.152727-8-s-vadapalli@ti.com (mailing list archive)
State New, archived
Headers show
Series Add PCIe and USB device-tree support for J722S | expand

Commit Message

s-vadapalli May 24, 2024, 9:05 a.m. UTC 
The PCIe0 instance of PCIe on TI's J722S SoC is a Gen3 single lane PCIe
controller. Add the device-tree nodes for it and enable it in Root Complex
mode of operation using Lane 0 of the Serdes1 instance of Serdes.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Current patch is v1. No changelog.

 arch/arm64/boot/dts/ti/k3-j722s-evm.dts   | 17 +++++++++++
 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 37 +++++++++++++++++++++++
 2 files changed, 54 insertions(+)

Comments

Roger Quadros May 28, 2024, 12:26 p.m. UTC | #1 
On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> The PCIe0 instance of PCIe on TI's J722S SoC is a Gen3 single lane PCIe
> controller. Add the device-tree nodes for it and enable it in Root Complex
> mode of operation using Lane 0 of the Serdes1 instance of Serdes.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> Current patch is v1. No changelog.
> 
>  arch/arm64/boot/dts/ti/k3-j722s-evm.dts   | 17 +++++++++++
>  arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 37 +++++++++++++++++++++++
>  2 files changed, 54 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index 16c6ab8ee07e..d2d7de5cfe27 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -416,6 +416,16 @@ serdes0_usb_link: phy@0 {
>  	};
>  };
>  
> +&serdes1 {
> +	serdes1_pcie_link: phy@0 {
> +		reg = <0>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_PCIE>;
> +		resets = <&serdes_wiz1 1>;
> +	};
> +};
> +
>  &usbss0 {
>  	ti,vbus-divider;
>  	status = "okay";
> @@ -439,3 +449,10 @@ &usb1 {
>  	phys = <&serdes0_usb_link>;
>  	phy-names = "cdns3,usb3-phy";
>  };
> +
> +&pcie0_rc {
> +	status = "okay";
> +	reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
> +	phys = <&serdes1_pcie_link>;
> +	phy-names = "pcie-phy";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> index 19a7e8413ad2..0b32893eb75e 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> @@ -4,6 +4,7 @@
>   * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
>   */
>  
> +#include <dt-bindings/phy/phy-cadence.h>
>  #include <dt-bindings/phy/phy-ti.h>
>  
>  /*
> @@ -96,6 +97,35 @@ serdes1: serdes@f010000 {
>  		};
>  	};
>  
> +	pcie0_rc: pcie@f102000 {

Please split PCIe node addition in  to separate patch. hopefully you can squash it with patches that
add USB, SERDES0 and SERDES1 to k3-j722s-main.dtsi.


> +		compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
> +		reg = <0x00 0x0f102000 0x00 0x1000>,
> +		      <0x00 0x0f100000 0x00 0x400>,
> +		      <0x00 0x0d000000 0x00 0x00800000>,
> +		      <0x00 0x68000000 0x00 0x00001000>;
> +		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> +		ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
> +			 <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
> +		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> +		interrupt-names = "link_state";
> +		interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
> +		device_type = "pci";
> +		max-link-speed = <3>;
> +		num-lanes = <1>;
> +		power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
> +		clock-names = "fck", "pcie_refclk";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		bus-range = <0x0 0xff>;
> +		vendor-id = <0x104c>;
> +		device-id = <0xb010>;
> +		cdns,no-bar-match-nbits = <64>;
> +		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
> +		msi-map = <0x0 &gic_its 0x0 0x10000>;
> +		status = "disabled";
> +	};
> +
>  	usbss1: usb@f920000 {
>  		compatible = "ti,j721e-usb";
>  		reg = <0x00 0x0f920000 0x00 0x100>;
> @@ -138,3 +168,10 @@ serdes_ln_ctrl: mux-controller@4080 {
>  				<0x10 0x3>; /* SERDES1 lane0 select */
>  	};
>  };
> +
> +&wkup_conf {
> +	pcie0_ctrl: pcie0-ctrl@4070 {
> +		compatible = "ti,j784s4-pcie-ctrl", "syscon";
> +		reg = <0x4070 0x4>;
> +	};
> +};
s-vadapalli May 28, 2024, 12:44 p.m. UTC | #2 
On Tue, May 28, 2024 at 03:26:11PM +0300, Roger Quadros wrote:

[...]

> >  
> > +#include <dt-bindings/phy/phy-cadence.h>
> >  #include <dt-bindings/phy/phy-ti.h>
> >  
> >  /*
> > @@ -96,6 +97,35 @@ serdes1: serdes@f010000 {
> >  		};
> >  	};
> >  
> > +	pcie0_rc: pcie@f102000 {
> 
> Please split PCIe node addition in  to separate patch. hopefully you can squash it with patches that
> add USB, SERDES0 and SERDES1 to k3-j722s-main.dtsi.

I will do so in the v4 series. Thank you for reviewing and sharing your
feedback on this series.

Regards,
Siddharth.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index 16c6ab8ee07e..d2d7de5cfe27 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -416,6 +416,16 @@  serdes0_usb_link: phy@0 {
 	};
 };
 
+&serdes1 {
+	serdes1_pcie_link: phy@0 {
+		reg = <0>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_PCIE>;
+		resets = <&serdes_wiz1 1>;
+	};
+};
+
 &usbss0 {
 	ti,vbus-divider;
 	status = "okay";
@@ -439,3 +449,10 @@  &usb1 {
 	phys = <&serdes0_usb_link>;
 	phy-names = "cdns3,usb3-phy";
 };
+
+&pcie0_rc {
+	status = "okay";
+	reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes1_pcie_link>;
+	phy-names = "pcie-phy";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 19a7e8413ad2..0b32893eb75e 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -4,6 +4,7 @@ 
  * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include <dt-bindings/phy/phy-cadence.h>
 #include <dt-bindings/phy/phy-ti.h>
 
 /*
@@ -96,6 +97,35 @@  serdes1: serdes@f010000 {
 		};
 	};
 
+	pcie0_rc: pcie@f102000 {
+		compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
+		reg = <0x00 0x0f102000 0x00 0x1000>,
+		      <0x00 0x0f100000 0x00 0x400>,
+		      <0x00 0x0d000000 0x00 0x00800000>,
+		      <0x00 0x68000000 0x00 0x00001000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+		ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
+			 <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
+		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
+		device_type = "pci";
+		max-link-speed = <3>;
+		num-lanes = <1>;
+		power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+		clock-names = "fck", "pcie_refclk";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x0 0xff>;
+		vendor-id = <0x104c>;
+		device-id = <0xb010>;
+		cdns,no-bar-match-nbits = <64>;
+		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+		msi-map = <0x0 &gic_its 0x0 0x10000>;
+		status = "disabled";
+	};
+
 	usbss1: usb@f920000 {
 		compatible = "ti,j721e-usb";
 		reg = <0x00 0x0f920000 0x00 0x100>;
@@ -138,3 +168,10 @@  serdes_ln_ctrl: mux-controller@4080 {
 				<0x10 0x3>; /* SERDES1 lane0 select */
 	};
 };
+
+&wkup_conf {
+	pcie0_ctrl: pcie0-ctrl@4070 {
+		compatible = "ti,j784s4-pcie-ctrl", "syscon";
+		reg = <0x4070 0x4>;
+	};
+};