diff mbox series

clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs

Message ID 20240508-stromer-plus-alpha-en-v1-1-6639ce01ca5b@gmail.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs | expand

Commit Message

Gabor Juhos May 8, 2024, 8:34 p.m. UTC
The clk_alpha_pll_stromer_plus_set_rate() function does not
sets the ALPHA_EN bit in the USER_CTL register, so setting
rates which requires using alpha mode works only if the bit
gets set already prior calling the function.

Extend the function to set the ALPHA_EN bit in order to allow
using fractional rates regardless whether the bit gets set
previously or not.

Fixes: 84da48921a97 ("clk: qcom: clk-alpha-pll: introduce stromer plus ops")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
Based on 'qcom-clk-for-6.10'
---

---
 drivers/clk/qcom/clk-alpha-pll.c | 3 +++
 1 file changed, 3 insertions(+)


---
base-commit: 3c5b3e17b8fd1f1add5a9477306c355fab126977
change-id: 20240508-stromer-plus-alpha-en-0a4a4c6df28c

Best regards,

Comments

Bjorn Andersson May 29, 2024, 2:01 a.m. UTC | #1
On Wed, 08 May 2024 22:34:14 +0200, Gabor Juhos wrote:
> The clk_alpha_pll_stromer_plus_set_rate() function does not
> sets the ALPHA_EN bit in the USER_CTL register, so setting
> rates which requires using alpha mode works only if the bit
> gets set already prior calling the function.
> 
> Extend the function to set the ALPHA_EN bit in order to allow
> using fractional rates regardless whether the bit gets set
> previously or not.
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs
      commit: 5a33a64524e6381c399e5e42571d9363ffc0bed4

Best regards,
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index d4227909d1fe..c51647e37df8 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -2574,6 +2574,9 @@  static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
 	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
 					a >> ALPHA_BITWIDTH);
 
+	regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+			   PLL_ALPHA_EN, PLL_ALPHA_EN);
+
 	regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
 
 	/* Wait five micro seconds or more */