| Message ID | 20240528151052.313031-5-alexghiti@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Zacas/Zabha support and qspinlocks | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On Tue, May 28, 2024 at 05:10:49PM +0200, Alexandre Ghiti wrote: \ > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index e17d0078a651..f71ddd2ca163 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -81,6 +81,7 @@ > #define RISCV_ISA_EXT_ZTSO 72 > #define RISCV_ISA_EXT_ZACAS 73 > #define RISCV_ISA_EXT_XANDESPMU 74 > +#define RISCV_ISA_EXT_ZABHA 75 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 3ed2359eae35..8d0f56dd2f53 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -257,6 +257,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > + __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA), > __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), > __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), > __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), You're missing a dt-binding patch in this series adding zabha. Thanks, Conor.
> -#define __arch_xchg_masked(prepend, append, r, p, n) \ > +#define __arch_xchg_masked(swap_sfx, prepend, append, r, p, n) \ This actually indicates a problem in the current (aka, no Zabha) implementation: without your series, xchg16() gets mapped to lr.w a2,(a3) and a1,a2,a5 or a1,a1,a4 sc.w a1,a1,(a3) bnez a1,43c <.L0^B1> which is clearly wrong... (other "fully-ordered LR/SC sequences" instead follow the mapping lr.w a2,(a3) and a1,a2,a5 or a1,a1,a4 sc.w.rl a1,a1,(a3) bnez a1,43c <.L0^B1> fence rw,rw ) A similar consideration for xchg8(). Andrea
Hi Conor, On Tue, May 28, 2024 at 5:22 PM Conor Dooley <conor@kernel.org> wrote: > > On Tue, May 28, 2024 at 05:10:49PM +0200, Alexandre Ghiti wrote: > \ > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index e17d0078a651..f71ddd2ca163 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -81,6 +81,7 @@ > > #define RISCV_ISA_EXT_ZTSO 72 > > #define RISCV_ISA_EXT_ZACAS 73 > > #define RISCV_ISA_EXT_XANDESPMU 74 > > +#define RISCV_ISA_EXT_ZABHA 75 > > > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 3ed2359eae35..8d0f56dd2f53 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -257,6 +257,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > > __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), > > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > > + __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA), > > __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), > > __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), > > __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), > > You're missing a dt-binding patch in this series adding zabha. Thanks, I will add that to the v2. > > Thanks, > Conor.
Hi Andrea, On Tue, May 28, 2024 at 8:00 PM Andrea Parri <parri.andrea@gmail.com> wrote: > > > -#define __arch_xchg_masked(prepend, append, r, p, n) \ > > +#define __arch_xchg_masked(swap_sfx, prepend, append, r, p, n) \ > > This actually indicates a problem in the current (aka, no Zabha) > implementation: without your series, xchg16() gets mapped to > > lr.w a2,(a3) > and a1,a2,a5 > or a1,a1,a4 > sc.w a1,a1,(a3) > bnez a1,43c <.L0^B1> > > which is clearly wrong... (other "fully-ordered LR/SC sequences" > instead follow the mapping > > lr.w a2,(a3) > and a1,a2,a5 > or a1,a1,a4 > sc.w.rl a1,a1,(a3) > bnez a1,43c <.L0^B1> > fence rw,rw ) > > A similar consideration for xchg8(). Ok, I will fix that separately and make it merged in -rc2. Thanks, Akex > > Andrea
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 0789fbe38b23..43696d9e13aa 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -11,8 +11,14 @@ #include <asm/fence.h> #include <asm/alternative.h> -#define __arch_xchg_masked(prepend, append, r, p, n) \ +#define __arch_xchg_masked(swap_sfx, prepend, append, r, p, n) \ ({ \ + __label__ zabha, end; \ + \ + asm goto(ALTERNATIVE("nop", "j %[zabha]", 0, \ + RISCV_ISA_EXT_ZABHA, 1) \ + : : : : zabha); \ + \ u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \ ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \ ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \ @@ -34,6 +40,17 @@ : "memory"); \ \ r = (__typeof__(*(p)))((__retx & __mask) >> __s); \ + goto end; \ + \ +zabha: \ + __asm__ __volatile__ ( \ + prepend \ + " amoswap" swap_sfx " %0, %z2, %1\n" \ + append \ + : "=&r" (r), "+A" (*(p)) \ + : "rJ" (n) \ + : "memory"); \ +end: \ }) #define __arch_xchg(sfx, prepend, append, r, p, n) \ @@ -55,8 +72,11 @@ \ switch (sizeof(*__ptr)) { \ case 1: \ + __arch_xchg_masked(".b" sfx, prepend, append, \ + __ret, __ptr, __new); \ + break; \ case 2: \ - __arch_xchg_masked(prepend, append, \ + __arch_xchg_masked(".h" sfx, prepend, append, \ __ret, __ptr, __new); \ break; \ case 4: \ diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..f71ddd2ca163 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,7 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_ZABHA 75 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3ed2359eae35..8d0f56dd2f53 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -257,6 +257,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), + __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA), __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
This adds runtime support for Zabha in xchg8/16() operations. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> --- arch/riscv/include/asm/cmpxchg.h | 24 ++++++++++++++++++++++-- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 24 insertions(+), 2 deletions(-)