| Message ID | 20240527131541.1676525-4-niklas.soderlund+renesas@ragnatech.se (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: renesas: r8a779h0: Add clocks for video capture | expand |
Hi Niklas, On Mon, May 27, 2024 at 3:16 PM Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> wrote: > Add the CSI40 and CSI41 module clocks, which are used by the CSI-2 > interfaces on the Renesas R-Car V4M (R8A779H0) SoC. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Thanks for your patch! > --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > @@ -176,6 +176,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { > DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), > DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), > DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), > + DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), > + DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), According to the documentation for the Module Stop Control Registers 3 and 4, these are called "csitop[01]". > DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), > DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), > DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), Gr{oetje,eeting}s, Geert
Hi Geert, Thanks for your review. On 2024-05-29 17:09:09 +0200, Geert Uytterhoeven wrote: > Hi Niklas, > > On Mon, May 27, 2024 at 3:16 PM Niklas Söderlund > <niklas.soderlund+renesas@ragnatech.se> wrote: > > Add the CSI40 and CSI41 module clocks, which are used by the CSI-2 > > interfaces on the Renesas R-Car V4M (R8A779H0) SoC. > > > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > Thanks for your patch! > > > --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c > > +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > > @@ -176,6 +176,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { > > DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), > > DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), > > DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), > > + DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), > > + DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), > > According to the documentation for the Module Stop Control Registers > 3 and 4, these are called "csitop[01]". I noticed that too, the issue is how they are named on V4H and I thought aligning the Gen4 board was a good idea. I don't feel strongly about this, but before I send a v2. On V4H the bits are named SRT31 and SRT0, while the "Target Module for Software Reset" lists them as "CSI40 (CSI-2-RX0)" and "CSI40 (CSI-2-RX1)". The later is the same for V4H and V4M, while the bit name differs. Should we rename the V4H modules as well, keep the names for V4M, or do we not really care the same modules have different names on V4H and V4M? > > > DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), > > DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), > > DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
Hi Niklas, On Wed, May 29, 2024 at 5:30 PM Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> wrote: > On 2024-05-29 17:09:09 +0200, Geert Uytterhoeven wrote: > > On Mon, May 27, 2024 at 3:16 PM Niklas Söderlund > > <niklas.soderlund+renesas@ragnatech.se> wrote: > > > Add the CSI40 and CSI41 module clocks, which are used by the CSI-2 > > > interfaces on the Renesas R-Car V4M (R8A779H0) SoC. > > > > > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > > > Thanks for your patch! > > > > > --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c > > > +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > > > @@ -176,6 +176,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { > > > DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), > > > DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), > > > DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), > > > + DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), > > > + DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), > > > > According to the documentation for the Module Stop Control Registers > > 3 and 4, these are called "csitop[01]". > > I noticed that too, the issue is how they are named on V4H and I thought > aligning the Gen4 board was a good idea. I don't feel strongly about > this, but before I send a v2. > > On V4H the bits are named SRT31 and SRT0, while the "Target Module for > Software Reset" lists them as "CSI40 (CSI-2-RX0)" and "CSI40 > (CSI-2-RX1)". The later is the same for V4H and V4M, while the bit name > differs. > > Should we rename the V4H modules as well, keep the names for V4M, or do > we not really care the same modules have different names on V4H and V4M? We already have other differences due to how the bits are named in (different revisions of) the different datasheets... Technically, nobody really cares about these clocks names, they just must be unique ;-) And apparently older revisions of the R-Car V4H docs use "csitop[01]", too. Oh well... I guess I'll just apply this as-is, unless someone screams... Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk for v6.11. Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 7f8e0e71a8b4..b3cc86bb36ec 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -176,6 +176,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), + DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), + DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
Add the CSI40 and CSI41 module clocks, which are used by the CSI-2 interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> --- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+)