diff mbox series

irqchip/gic: Use smp_wmb() instead of dmb(ishst)

Message ID 20240530005254.1495461-1-samuel.holland@sifive.com (mailing list archive)
State New, archived
Headers show
Series irqchip/gic: Use smp_wmb() instead of dmb(ishst) | expand

Commit Message

Samuel Holland May 30, 2024, 12:52 a.m. UTC
This is equivalent on ARM, but also works on other architectures.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

 drivers/irqchip/irq-gic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Marc Zyngier May 30, 2024, 8:59 a.m. UTC | #1
On Thu, 30 May 2024 01:52:30 +0100,
Samuel Holland <samuel.holland@sifive.com> wrote:
> 
> This is equivalent on ARM, but also works on other architectures.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
> 
>  drivers/irqchip/irq-gic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index 98aa383e39db..dc2e4018a40c 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -839,7 +839,7 @@ static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
>  	 * Ensure that stores to Normal memory are visible to the
>  	 * other CPUs before they observe us issuing the IPI.
>  	 */
> -	dmb(ishst);
> +	smp_wmb();
>  
>  	/* this always happens on GIC0 */
>  	writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);

Equivalent, sure. But what does it gain us, given that the driver is
only compiled on ARM systems?

Additionally, you may also want to address the one in the hip04
driver, which has the same dmb instruction.

Thanks,

	M.
diff mbox series

Patch

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 98aa383e39db..dc2e4018a40c 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -839,7 +839,7 @@  static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
 	 * Ensure that stores to Normal memory are visible to the
 	 * other CPUs before they observe us issuing the IPI.
 	 */
-	dmb(ishst);
+	smp_wmb();
 
 	/* this always happens on GIC0 */
 	writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);