| Message ID | 20240531-x1e80100-phy-add-gen4x4-v1-1-5c841dae7850@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | phy: qcom: qmp-pcie: Add support for Gen4 4-lane mode for X1E80100 | expand |
On 31/05/2024 18:06, Abel Vesa wrote: > The PCIe 6th instance from X1E80100 can be used in both 4-lane mode or > 2-lane mode. Document the 4-lane mode as a separate compatible. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
On Fri, May 31, 2024 at 07:06:44PM +0300, Abel Vesa wrote: > The PCIe 6th instance from X1E80100 can be used in both 4-lane mode or nit: s/PCIe 6th/sixth PCIe/ nit: s/from/on/ nit: s/both/either/ > 2-lane mode. Document the 4-lane mode as a separate compatible. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Johan
On 03/06/2024 14:43, Johan Hovold wrote: > On Fri, May 31, 2024 at 07:06:44PM +0300, Abel Vesa wrote: >> The PCIe 6th instance from X1E80100 can be used in both 4-lane mode or > > nit: s/PCIe 6th/sixth PCIe/ > nit: s/from/on/ > nit: s/both/either/ That's really nit-picking and not helpful in getting things merged. Best regards, Krzysztof
On Tue, Jun 04, 2024 at 01:00:35PM +0200, Krzysztof Kozlowski wrote: > On 03/06/2024 14:43, Johan Hovold wrote: > > On Fri, May 31, 2024 at 07:06:44PM +0300, Abel Vesa wrote: > >> The PCIe 6th instance from X1E80100 can be used in both 4-lane mode or > > > > nit: s/PCIe 6th/sixth PCIe/ > > nit: s/from/on/ > > nit: s/both/either/ > > That's really nit-picking and not helpful in getting things merged. Writing proper commit messages with correct grammar is in no way to be asking too much (especially from experienced kernel devs). Also, the code does not work so it should not be merged yet anyway. Johan
On 04/06/2024 13:17, Johan Hovold wrote: > On Tue, Jun 04, 2024 at 01:00:35PM +0200, Krzysztof Kozlowski wrote: >> On 03/06/2024 14:43, Johan Hovold wrote: >>> On Fri, May 31, 2024 at 07:06:44PM +0300, Abel Vesa wrote: >>>> The PCIe 6th instance from X1E80100 can be used in both 4-lane mode or >>> >>> nit: s/PCIe 6th/sixth PCIe/ >>> nit: s/from/on/ >>> nit: s/both/either/ >> >> That's really nit-picking and not helpful in getting things merged. > > Writing proper commit messages with correct grammar is in no way to be > asking too much (especially from experienced kernel devs). Well, many of us are not native English speakers, so when the commit msg is 100% understandable, pointing out grammar mistakes or style (6th->sixth) issues is nit-picking and is asking for unnecessary work. > > Also, the code does not work so it should not be merged yet anyway. OK Best regards, Krzysztof
On 24-06-03 14:43:15, Johan Hovold wrote: > On Fri, May 31, 2024 at 07:06:44PM +0300, Abel Vesa wrote: > > The PCIe 6th instance from X1E80100 can be used in both 4-lane mode or > > nit: s/PCIe 6th/sixth PCIe/ > nit: s/from/on/ > nit: s/both/either/ > Thanks for reviewing. Will address them in the next version. > > 2-lane mode. Document the 4-lane mode as a separate compatible. > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > Johan
On Tue, Jun 04, 2024 at 01:37:46PM +0200, Krzysztof Kozlowski wrote: > On 04/06/2024 13:17, Johan Hovold wrote: > > On Tue, Jun 04, 2024 at 01:00:35PM +0200, Krzysztof Kozlowski wrote: > >> On 03/06/2024 14:43, Johan Hovold wrote: > >>> On Fri, May 31, 2024 at 07:06:44PM +0300, Abel Vesa wrote: > >>>> The PCIe 6th instance from X1E80100 can be used in both 4-lane mode or > >>> > >>> nit: s/PCIe 6th/sixth PCIe/ > >>> nit: s/from/on/ > >>> nit: s/both/either/ > >> > >> That's really nit-picking and not helpful in getting things merged. > > > > Writing proper commit messages with correct grammar is in no way to be > > asking too much (especially from experienced kernel devs). > > Well, many of us are not native English speakers, so when the commit msg > is 100% understandable, pointing out grammar mistakes or style > (6th->sixth) issues is nit-picking and is asking for unnecessary work. Well I did use a "nit:" prefix for a reason. And I hope people are still interested in improving their English even if it's not their first language. Johan
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 16634f73bdcf..f96f692c9ee5 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -40,6 +40,7 @@ properties: - qcom,sm8650-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen3x2-pcie-phy - qcom,x1e80100-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy reg: minItems: 1 @@ -119,6 +120,7 @@ allOf: contains: enum: - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy then: properties: reg: @@ -170,6 +172,7 @@ allOf: - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy then: properties: clocks:
The PCIe 6th instance from X1E80100 can be used in both 4-lane mode or 2-lane mode. Document the 4-lane mode as a separate compatible. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 +++ 1 file changed, 3 insertions(+)