| Message ID | 20240511-mips-clks-v1-1-ddb4a10ee9f9@flygoat.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | MIPS: clocksource cumulative enhancements | expand |
On Sat, 11 May 2024, Jiaxun Yang wrote: > Increase frequency addend dividend to 100000000 (10MHz) to The value of 100000000 is AFAICT 100MHz. > diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c > index edc4afc080fa..262896871351 100644 > --- a/arch/mips/kernel/csrc-r4k.c > +++ b/arch/mips/kernel/csrc-r4k.c > @@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void) > return -ENXIO; > > /* Calculate a somewhat reasonable rating value */ > - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; > + clocksource_mips.rating = 200; > + clocksource_mips.rating += clamp(mips_hpt_frequency / 100000000, 0, 99); And FAOD the code change does match it. Maciej
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index edc4afc080fa..262896871351 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void) return -ENXIO; /* Calculate a somewhat reasonable rating value */ - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; + clocksource_mips.rating = 200; + clocksource_mips.rating += clamp(mips_hpt_frequency / 100000000, 0, 99); /* * R2 onwards makes the count accessible to user mode so it can be used
Increase frequency addend dividend to 100000000 (10MHz) to reasonably accommodate multi GHz level mips_hpt_frequency. Cap rating of csrc-r4k into 299 to ensure it doesn't go into "Desired" range, given all the drama we have with CP0 count registers (SMP sync, behaviour on wait etc). Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- arch/mips/kernel/csrc-r4k.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)