| Message ID | eed30cb59cc45955a88cdf951023b0e695095760.1717514638.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: finish the job of removing implicit dev_priv | expand |
On Tue, Jun 04, 2024 at 06:25:26PM +0300, Jani Nikula wrote: > Avoid the implicit dev_priv local variable use, and pass dev_priv > explicitly to the TRANS_VSYNC register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++- > drivers/gpu/drm/i915/display/intel_crt.c | 3 ++- > drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- > 6 files changed, 13 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index 0ee42954054f..b267099fde8a 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -967,7 +967,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, > if (is_vid_mode(intel_dsi)) { > for_each_dsi_port(port, intel_dsi->ports) { > dsi_trans = dsi_port_to_transcoder(port); > - intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans), > + intel_de_write(dev_priv, > + TRANS_VSYNC(dev_priv, dsi_trans), > VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); > } > } > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c > index 54549d2cfcff..15569cf96c9c 100644 > --- a/drivers/gpu/drm/i915/display/intel_crt.c > +++ b/drivers/gpu/drm/i915/display/intel_crt.c > @@ -746,7 +746,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) > * Yes, this will flicker > */ > if (vblank_start <= vactive && vblank_end >= vtotal) { > - u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); > + u32 vsync = intel_de_read(dev_priv, > + TRANS_VSYNC(dev_priv, cpu_transcoder)); > u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; > > vblank_start = vsync_start; > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 87a690cf5808..776e4450e4af 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2726,7 +2726,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta > intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), > VBLANK_START(crtc_vblank_start - 1) | > VBLANK_END(crtc_vblank_end - 1)); > - intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), > + intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), > VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | > VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); > > @@ -2837,7 +2837,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, > adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; > adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; > } > - tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); > + tmp = intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)); > adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; > adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; > > @@ -8201,7 +8201,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) > VACTIVE(480 - 1) | VTOTAL(525 - 1)); > intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), > VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); > - intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), > + intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), > VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); > intel_de_write(dev_priv, PIPESRC(pipe), > PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c > index 03a33ff2653a..9f8269705171 100644 > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c > @@ -235,7 +235,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s > intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), > intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder))); > intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), > - intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder))); > + intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder))); > intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), > intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder))); > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 155259c11c88..c47aae3f70cd 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1222,7 +1222,7 @@ > #define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) > #define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) > #define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) > -#define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) > +#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) > #define BCLRPAT(trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) > #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) > #define PIPESRC(pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > index baeedcdfdcab..e618a16eafac 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -236,7 +236,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) > MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A)); > MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A)); > MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A)); > - MMIO_D(TRANS_VSYNC(TRANSCODER_A)); > + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A)); > MMIO_D(BCLRPAT(TRANSCODER_A)); > MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A)); > MMIO_D(PIPESRC(TRANSCODER_A)); > @@ -245,7 +245,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) > MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B)); > MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B)); > MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B)); > - MMIO_D(TRANS_VSYNC(TRANSCODER_B)); > + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B)); > MMIO_D(BCLRPAT(TRANSCODER_B)); > MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B)); > MMIO_D(PIPESRC(TRANSCODER_B)); > @@ -254,7 +254,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) > MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C)); > MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C)); > MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C)); > - MMIO_D(TRANS_VSYNC(TRANSCODER_C)); > + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C)); > MMIO_D(BCLRPAT(TRANSCODER_C)); > MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C)); > MMIO_D(PIPESRC(TRANSCODER_C)); > @@ -263,7 +263,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) > MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP)); > MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP)); > MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP)); > - MMIO_D(TRANS_VSYNC(TRANSCODER_EDP)); > + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP)); > MMIO_D(BCLRPAT(TRANSCODER_EDP)); > MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP)); > MMIO_D(PIPE_DATA_M1(TRANSCODER_A)); > -- > 2.39.2 >
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 0ee42954054f..b267099fde8a 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -967,7 +967,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, if (is_vid_mode(intel_dsi)) { for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans), + intel_de_write(dev_priv, + TRANS_VSYNC(dev_priv, dsi_trans), VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); } } diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 54549d2cfcff..15569cf96c9c 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -746,7 +746,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) * Yes, this will flicker */ if (vblank_start <= vactive && vblank_end >= vtotal) { - u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); + u32 vsync = intel_de_read(dev_priv, + TRANS_VSYNC(dev_priv, cpu_transcoder)); u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; vblank_start = vsync_start; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 87a690cf5808..776e4450e4af 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2726,7 +2726,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), VBLANK_START(crtc_vblank_start - 1) | VBLANK_END(crtc_vblank_end - 1)); - intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); @@ -2837,7 +2837,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; } - tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); + tmp = intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)); adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; @@ -8201,7 +8201,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) VACTIVE(480 - 1) | VTOTAL(525 - 1)); intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); - intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); intel_de_write(dev_priv, PIPESRC(pipe), PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 03a33ff2653a..9f8269705171 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -235,7 +235,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), - intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder))); + intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder))); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 155259c11c88..c47aae3f70cd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1222,7 +1222,7 @@ #define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) #define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) #define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) -#define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) +#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) #define BCLRPAT(trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) #define PIPESRC(pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index baeedcdfdcab..e618a16eafac 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -236,7 +236,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A)); - MMIO_D(TRANS_VSYNC(TRANSCODER_A)); + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A)); MMIO_D(BCLRPAT(TRANSCODER_A)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A)); MMIO_D(PIPESRC(TRANSCODER_A)); @@ -245,7 +245,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B)); - MMIO_D(TRANS_VSYNC(TRANSCODER_B)); + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B)); MMIO_D(BCLRPAT(TRANSCODER_B)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B)); MMIO_D(PIPESRC(TRANSCODER_B)); @@ -254,7 +254,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C)); - MMIO_D(TRANS_VSYNC(TRANSCODER_C)); + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C)); MMIO_D(BCLRPAT(TRANSCODER_C)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C)); MMIO_D(PIPESRC(TRANSCODER_C)); @@ -263,7 +263,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP)); - MMIO_D(TRANS_VSYNC(TRANSCODER_EDP)); + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP)); MMIO_D(BCLRPAT(TRANSCODER_EDP)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VSYNC register macro. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++- drivers/gpu/drm/i915/display/intel_crt.c | 3 ++- drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 6 files changed, 13 insertions(+), 11 deletions(-)